WB_LCDCTRL_SRAM - Pin Description
The following pin description is for the WB_LCDCTRL_SRAM when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. WB_LCDCTRL_SRAM Pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock |
| RST_I | I | High | External (system) reset |
| Wishbone Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes High, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | Level | Address bus. For the WB_LCDCTRL_SRAM, this input is used to directly control the state of the data/instruction select signal to the LCD panel: 0 = Instruction (access panel's Control register) Note: When communicating with the LCD panel, the value at ADR_I appears as bit 0 of the MEM_ADDR bus |
| DAT_O | O | 8 | Data to be sent to host processor |
| DAT_I | I | 8 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| Memory Controller Interface Signals | |||
| CTRL0_D | IO | 8 | Data Bus for SRAM module 0 |
| CTRL1_D | IO | 8 | Data Bus for SRAM module 1 |
| CTRL_CE | I | Low | Memory Chip Enable. This signal is shared by the NB1's two SRAM modules |
| CTRL_A | I | 17 | Memory Address Bus. This bus is shared by the NB1's two SRAM modules and provides access to either modules' 128K address space |
| CTRL0_WE | I | Low | Write Enable for SRAM module 0 -- active when performing a write to an addressed location in the memory address space for SRAM module 0. This input is internally connected directly to the MEM0_WE output. |
| CTRL1_WE | I | Low | Write Enable for SRAM module 1 -- active when performing a write to an addressed location in the memory address space for SRAM module 1. This input is internally connected directly to the MEM1_WE output. |
| CTRL0_OE | I | Low | Output Enable for SRAM module 0 -- active when performing a read from an addressed location in the memory address space for SRAM module 0. This input is internally connected directly to the MEM0_OE output. |
| CTRL1_OE | I | Low | Output Enable for SRAM module 1 -- active when performing a read from an addressed location in the memory address space for SRAM module 1. This input is internally connected directly to the MEM1_OE output. |
| LCD Panel/SRAM Interface Signals | |||
| LCD_E | O | High | Enable signal to the LCD panel (corresponds to E pin on most LCD panels). |
| MEM0_DATA | IO | 8 | Data Bus for SRAM module 0. When communicating with the LCD, this bus effectively becomes the LCD_DATA bus. When writing to the LCD, data is channeled from the DAT_I input to this bus. When reading from the LCD, data is channeled from this bus to the DAT_O line. |
| MEM1_DATA | IO | 8 | Data Bus for SRAM module 1 |
| MEM_CS | O | Low | Memory Chip Select. This signal is shared by the NB1's two SRAM modules. The state of this signal is controlled by the following logic expression: MEM_CS = CTRL_CE OR (STB_I AND CYC_I) Therefore, when communicating with SRAM, the output follows the CTRL_CE input. When the host is wishing to communicate with the LCD, this output will be disabled |
| MEM_ADDR | O | 17 | Memory Address Bus. This bus is shared by the NB1's two SRAM modules and provides access to either modules' 128K address space. When communicating with SRAM, the full 17-bit address appearing at the Controller's CTRL_A input is channeled through to the MEM_ADDR output. When communicating with the LCD, bits 16..2 of the CTRL_A input are channeled through to bits 16..2 of the MEM_ADDR bus. The lowest two bits of MEM_ADDR are assigned as follows: Bit 0 = the current state of ADR_I |
| MEM0_WE | O | Low | Write Enable for SRAM module 0 -- active when performing a write to an addressed location in the memory address space for SRAM module 0. Note: This signal directly follows the state of the CTRL0_WE input |
| MEM1_WE | O | Low | Write Enable for SRAM module 1 -- active when performing a write to an addressed location in the memory address space for SRAM module 1. Note: This signal directly follows the state of the CTRL1_WE input |
| MEM0_OE | O | Low | Output Enable for SRAM module 0 -- active when performing a read from an addressed location in the memory address space for SRAM module 0. Note: This signal directly follows the state of the CTRL0_OE input |
| MEM1_OE | O | Low | Output Enable for SRAM module 1 -- active when performing a read from an addressed location in the memory address space for SRAM module 1. Note: This signal directly follows the state of the CTRL1_OE input |