WB_LCDCTRL_SRAM - Operational Overview

The LCD Controller is implemented as a Finite State Machine, with a maximum operating frequency of 50 MHz.

The Cycle Counter is an internal 7-bit counter used to control transitions between certain states of the FSM.

The Internal Multiplexing is used to configure the Controller. By default, the WB_LCDCTRL_SRAM is configured for communications with SRAM (SRAM0 and SRAM1) – simply marshalling communications between the connected WB_MEM_CTRL on the one side and the physical SRAM on the other. To communicate with the LCD panel, the host processor must initiate a write or read cycle, as required, over the Wishbone interface.

State Machine Operation (LCD Communications)

The Controller's FSM has 6 states. The operation of the FSM can be summarized as follows and is particularly useful as it indicates the length of a complete read/write cycle and the minimum time between consecutive cycles:

• State 1 (Address Setup) – this is the initial state for the Controller. The Controller resets the Cycle Counter to 0000000 in this state and will remain in this state until the host processor takes the STB_I and CYC_I lines High.

• State 2 (Setup Delay 1) – this state simply provides a delay of one clock cycle (CLK_I)

• State 3 (Setup Delay 2) – this state simply provides a delay of one clock cycle (CLK_I)

• State 4 (Enable LCD) – in this state, the LCD_E output is taken High (thus enabling the LCD panel). The Controller remains in this state until the Cycle Counter reaches a count of 15 (300ns @ 50MHz)

• State 5 (Acknowledge) – in this state, the Controller takes its ACK_O output High, signifying to the host processor that the requested task has been carried out. If performing a write operation, the LCD_E output will be taken Low at this time. If performing a read operation, the LCD_E output will remain High until the read is complete. The host will capture the data one cycle after the ACK_O signal is taken High. The Controller also resets the Cycle Counter to 0000000 in this state

• State 6 (Post Acknowledge Delay) – this state simply provides a delay of 80 clock cycles (1600ns @ 50MHz), after which time the Controller enters the initial Address Setup state and a new read/write cycle can begin.

Reading/Writing SRAM Address Space

If the STB_I and CYC_I inputs are not High, the host is not requesting communications with the LCD panel and the WB_LCDCTRL_SRAM is left configured for communication with SRAM address space. The full 17-bit address on the CTRL_A bus is passed to the MEM_ADDR bus. The chanelling of data then depends on whether the operation is a read or write access to the memory space and also, which SRAM module is being read/written:

• Reading the SRAM0 module – In this case, the MEM0_DATA bus is set to high impedance state, after which data from the addressed memory location in the SRAM0 module's address space is made available directly on the CTRL0_D bus. From here, it is read by the connected WB_MEM_CTRL device.

• Writing the SRAM0 module – In this case, data present on the CTRL0_D bus is made available directly on the MEM0_DATA bus and sent to the addressed memory location in the SRAM0 module's address space. The CTRL0_D bus is then set in a high impedance state.

• Reading the SRAM1 module – In this case, the MEM1_DATA bus is set to high impedance state, after which data from the addressed memory location in the SRAM1 module's address space is passed over the MEM1_DATA bus and made available on the CTRL1_D bus. From here, it is read by the connected WB_MEM_CTRL device.

• Writing the SRAM1 module – In this case, data present on the CTRL1_D bus is made available on the MEM1_DATA bus and sent to the addressed memory location in the SRAM1 module's address space. The CTRL1_D bus is then set in a high impedance state.

If STB_I and CYC_I are taken High, the host processor is wishing to read/write the LCD panel's memory (which is the same memory space as the SRAM). MEM_ADDR[0] is set to the state of ADR_I. MEM_ADDR[1] is set to '1' if a read operation is being performed, or '0' for a write operation.

The CTRL0_D bus is placed in a high impedance state. If writing, the data present on the DAT_I bus is made available directly on the MEM0_DATA bus, otherwise the MEM0_DATA bus is placed in the high impedance state.

The MEM0_DATA bus is connected directly to the DAT_O bus for presentation of LCD data during a read operation.