WB_LCDCTRL_SRAM - Host to Controller Communications

The following sections detail the standard handshaking that takes place when the host processor communicates with the WB_LCDCTRL_SRAM over the Wishbone interface, with a view to writing data to/reading data from the LCD panel.

Writing Data to the WB_LCDCTRL_SRAM

Data is written from the host processor (Wishbone Master) to the WB_LCDCTRL_SRAM (Wishbone Slave), in accordance with the standard Wishbone data transfer handshaking protocol. The write operation occurs on the rising edge of the CLK_I signal and can be summarized as follows:

• The host takes its ADR_O output High and presents a valid byte of data on its DAT_O output. It then asserts its WE_O signal, to specify a Write cycle.

• The WB_LCDCTRL_SRAM, receiving a High at its ADR_I input, takes bit 0 of the MEM_ADDR line High, signifying to the connected LCD panel that a data operation is imminent.

• The host asserts its STB_O and CYC_O outputs, indicating that the transfer is to begin. The WB_LCDCTRL_SRAM, which monitors its STB_I and CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by taking bit 1 of the MEM_ADDR line Low. The LCD_E output is taken High and the byte of data appearing at its DAT_I input is sent to the LCD panel over the MEM0_DATA bus. After an amount of time specified by the FSM, the Controller asserts its ACK_O signal – to indicate to the host that the data has been received by the LCD panel.

• The host, which monitors its ACK_I input on each rising edge of the CLK_I signal, responds by negating the STB_O and CYC_O signals. At the same time, the WB_LCDCTRL_SRAM negates the ACK_O signal and the data transfer cycle is naturally terminated.

Reading Data from the WB_LCDCTRL_SRAM

Data is read by the host processor (Wishbone Master) from the WB_LCDCTRL_SRAM (Wishbone Slave), in accordance with the standard Wishbone data transfer handshaking protocol. The read operation occurs on the rising edge of the CLK_I signal and can be summarized as follows:

• The host takes its ADR_O output High and negates its WE_O signal to specify a Read cycle.

• The WB_LCDCTRL_SRAM, receiving a High at its ADR_I input, takes bit 0 of the MEM_ADDR line High, signifying to the connected LCD panel that a data operation is imminent.

• The host asserts its STB_O and CYC_O outputs, indicating that the transfer is to begin. The WB_LCDCTRL_SRAM, which monitors its STB_I and CYC_I inputs on each rising edge of the CLK_I signal, reacts to this assertion by taking bit 1 of the MEM_ADDR line High. The LCD_E output is taken High and data is read from the LCD panel over the MEM0_DATA bus. This data is channeled through to the Controller's DAT_O output. After an amount of time specified by the FSM, the Controller asserts its ACK_O signal – to indicate to the host that valid data is present.

• The host, which monitors its ACK_I input on each rising edge of the CLK_I signal, responds by latching the byte of data appearing at its DAT_I input and negating the STB_O and CYC_O signals. At the same time, the WB_LCDCTRL_SRAM negates the ACK_O signal and the data transfer cycle is naturally terminated.