WB_IRRC - Operational Overview

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Modified by Admin on Sep 13, 2017

Operation of the WB_IRRC can be broken down into three main areas – initialization, data reception and data transmission. The following sections take a closer look at these areas.

Initialization

After an external reset (RST_I input goes High), you will need to initialize the WB_IRRC. (Note: The WB_IRRC automatically ensures the TFDU6102 FIR Transceiver is set to operate in remote control compatible SIR mode).

Initialization should be carried out in accordance with design requirements and can include:

Loading the Clock Divider register with the value required to generate the desired carrier frequency, that is to be used in the modulation/demodulation of IR signals.

Enabling external interrupts to the processor, if required, by setting the inten bit in the Control register (CTRL.0).

Configuring the mode of the peripheral – using the codec1 and codec0 bits of the Control register (CTRL.7 and CTRL.6) – and therefore switching it on:
- To operate in NEC Encoder/Decoder mode, ensure bits codec1 and codec0 are '0' and '1' respectively.
- To operate in RC5 Decoder mode, ensure bits codec1 and codec0 are '1' and '0' respectively.
- To operate in RAW Interface mode, ensure that both codec1 and codec0 are '0'.

If, after initialization, you write to the Clock Divider register, an internal reset will be issued and you will need to re-initialize the Control register.

Data Reception

The way in which data is received and processed depends on the operational mode set for the peripheral. The following sections look at data reception for each of the three operational modes – NEC Encoder/Decoder, RC5 Decoder and RAW Interface.

NEC Encoder/Decoder Mode

Let us consider the reception of IR RC data, transmitted using the NEC IR transmission protocol. We will assume that the WB_IRRC has been initialized and set to operate in NEC Encoder/Decoder mode.

The modulated IR data signal from the IR Transceiver is first demodulated, by passing it to the Pulse Detection Unit. The RXD input is active Low, which means that a space will appear as a logical '1' and a mark will appear as a logical '0'. The output of the Pulse Detection Unit is an inverted logic data stream where a space is represented as logical '0' and a pulse is represented as logical '1'. The current value of the demodulated signal is reflected in the rxpdet bit of the Status register (STATUS.1).

Data is received into an internal Receive Shift register (RX_SHIFT).

If it is a valid data command from the remote controller, the data will be decoded and the 32-bit value copied to the internal NEC_DATA register. The rxint bit in the Status register (STATUS.0) will be set to flag the availability of new command data.

If a repeat code has been received (the same button on the remote controller has been held down), then the rxrepeat bit in the Status register (STATUS.3) will also be set to flag a valid repeat code has arrived.

Provided the inten bit in the Control register (CTRL.0) is set, the processor can wait for the interrupt line to be taken High, signifying a valid remote command. Alternatively, it can actively poll the rxint and rxrepeat flags in the Status register.

The processor can jump to it's respective software routine for handling the new command or the repeat code. If the former, it should perform a read of the WB_IRRC's Data register address, and access the 32-bit data word stored in the internal NEC_DATA register.

As part of the handling routine the processor should, after the data has been retrieved or repeat code noted, send an acknowledgement – writing a '1' to the rxintrst bit in the Control register (CTRL.1). This will clear the rxintrst bit, as well as the rxint flag in the Status register (STATUS.0). If interrupts are enabled (inten bit in the Control register (CTRL.0) is set), then the INT_O line will also be taken Low.

If the received data is not acknowledged and rxint is left set, then when a new data command (or repeat code) from the remote controller is received, the rxoverrun flag in the Status register (STATUS.2) will become set, to indicate an overrun state, and the received data will be lost. You will need to first clear the rxint flag – by writing a '1' to the rxintrst bit in the Control register – before any more received and decoded data can be made available in the NEC_DATA register.

Remember that when reading data stored in the NEC_DATA register, the 32-bit value will contain the actual address and command bytes, as well as their inverses. The value in the NEC_DATA register will therefore be comprised as follows:

Consider, for example, using the Altium Remote Controller to send the "STOP" command (52h or 01010010b) to the design running in a daughter board FPGA on the Desktop NanoBoard NB2DSK01. The address used to target the IR Transceiver on the attached peripheral board PB03, is 00000000.

The decoded content of the NEC_DATA register will be:

The code running on the processor within the design may take just the command value from this word, for further processing or, more typically, use the entire 32-bit value and compare it against a pre-determined table of values – one of which will be designated the value associated with the "STOP" command. The code will then proceed with the relevant action to take.

RC5 Decoder Mode

Let us consider the reception of IR RC data, transmitted using the Philips RC5 IR transmission protocol. We will assume that the WB_IRRC has been initialized and set to operate in RC5 Decoder mode.

The modulated IR data signal from the IR Transceiver is first demodulated, by passing it to the Pulse Detection Unit. The RXD input is active Low, which means that a space will appear as a logical '1' and a mark will appear as a logical '0'. The output of the Pulse Detection Unit is an inverted logic data stream where a space is represented as logical '0' and a pulse is represented as logical '1'. The current value of the demodulated signal is reflected in the rxpdet bit of the Status register (STATUS.1).

Data is received into an internal Receive Shift register (RX_SHIFT).

If it is a valid data command from the remote controller, the data will be decoded and the 14-bit value copied to bits 13..0 of the internal RC5_DATA register. The rxint bit in the Status register (STATUS.0) will be set to flag the availability of new command data.

If the received command data is the same as the previously received command data (the same button on the remote controller has been held down), then the rxrepeat bit in the Status register (STATUS.3) will also be set to flag repeated data.

Provided the inten bit in the Control register (CTRL.0) is set, the processor can wait for the interrupt line to be taken High, signifying a valid remote command. Alternatively, it can actively poll the rxint and rxrepeat flags in the Status register.

The processor can jump to it's respective software routine for handling the new command or the repeated command. If the former, it should perform a read of the WB_IRRC's Data register address, and access the 14-bit data value stored in the internal RC5_DATA register.

As part of the handling routine the processor should, after the data has been retrieved or repeat data noted, send an acknowledgement – writing a '1' to the rxintrst bit in the Control register (CTRL.1). This will clear the rxintrst bit, as well as the rxint flag in the Status register (STATUS.0). If interrupts are enabled (inten bit in the Control register (CTRL.0) is set), then the INT_O line will also be taken Low.

If the received data is not acknowledged and rxint is left set, then when a new data command from the remote controller is received, the rxoverrun flag in the Status register (STATUS.2) will become set, to indicate an overrun state, and the received data will be lost. You will need to first clear the rxint flag – by writing a '1' to the rxintrst bit in the Control register – before any more received and decoded data can be made available in the RC5_DATA register.

Remember that when reading data stored in the RC5_DATA register, the 14-bit value will contain the address and command, as well as the Start (S1, S2) and Toggle (T) bits. The value in the RC5_DATA register will therefore be comprised as follows:

Consider, for example, using a Philips RC5 Remote Controller to send the "STOP" command (36h or 110110b) to the design running in a daughter board FPGA on the Desktop NanoBoard NB2DSK01. The address used to target the IR Transceiver on the attached peripheral board PB03, is 00000.

The decoded content of the RC5_DATA register will be:

The code running on the processor within the design may take just the command value from this word, for further processing or, more typically, use the entire 14-bit value and compare it against a pre-determined table of values – one of which will be designated the value associated with the "STOP" command. The code will then proceed with the relevant action to take.

RAW Interface Mode

Let us consider the reception of IR RC data, transmitted using an IR transmission protocol other than NEC or Philips RC5. We will assume that the WB_IRRC has been initialized and set to operate in RAW Interface mode.

The modulated IR data signal from the IR Transceiver is first demodulated, by passing it to the Pulse Detection Unit. The RXD input is active Low, which means that a space will appear as a logical '1' and a mark will appear as a logical '0'. The output of the Pulse Detection Unit is an inverted logic data stream where a space is represented as logical '0' and a pulse is represented as logical '1'. The current value of the demodulated signal is reflected in the rxpdet bit of the Status register (STATUS.1).

Data is received into an internal Receive Shift register (RX_SHIFT).

The demodulated signal is polled internally and an interrupt is generated for the next rising or falling edge – the rxint bit in the Status register (STATUS.0) is set.

The data is copied to the internal RAW_DATA register at each edge transition, reflecting the number of clock periods elapsed since the previous transition. The length for a pulse burst (mark) is loaded into the high-order word of the register, while the length for a space is loaded into the low-order word. This value can be used by edge handling routines in software to determine whether the full command data has been received.

Provided the inten bit in the Control register (CTRL.0) is set, the processor can wait for the interrupt line to be taken High. Alternatively, it can actively poll the rxint flag in the Status register.

The processor can then jump to it's respective software routine for handling a transition. It should perform a read of the WB_IRRC's Data register address, and access the 32-bit data word stored in the internal RAW_DATA register. For a rising edge, the length of the space will be reflected in bits 15..0 of the register. For a falling edge, the length of the pulse burst (mark) will be reflected in bits 31..0 of the register. Polling the rxpdet flag in the Status register (STATUS.1) will reveal the transition.

This routine will build the data word – still in encoded format.

As part of the handling routine the processor should, after the time data has been retrieved, send an acknowledgement - writing a '1' to the rxintrst bit in the Control register (CTRL.1). This will clear the rxintrst bit, as well as the rxint flag in the Status register (STATUS.0). If interrupts are enabled (inten bit in the Control register (CTRL.0) is set), then the INT_O line will also be taken Low.

The encoded data should then be passed to a decoding routine to generate the final decoded message.

If the length data for the current edge transition is not acknowledged and rxint is left set, then when the next edge transition of rxpdet occurs, the rxoverrun flag in the Status register (STATUS.2) will become set, to indicate an overrun state, and the new length data will be lost. You will need to first clear the rxint flag – by writing a '1' to the rxintrst bit in the Control register – before any more data can be made available in the RAW_DATA register.

Data Transmission

The way in which data is transmitted depends on the operational mode set for the peripheral. The following sections look at data transmission for the NEC Encoder/Decoder and RAW Interface modes.

NEC Encoder/Decoder Mode

Let us consider the transmission of IR RC data using the NEC IR transmission protocol. We will assume that the WB_IRRC has been initialized and set to operate in NEC Encoder/Decoder mode.

To transmit a new remote control code, simply poll the Status register. When the txbusy bit (STATUS.4) is cleared, write the 32-bit message data to the WB_IRRC's Data register address – the data will be loaded into the internal TX_DATA register.

Remember that when transmitting data using the NEC IR transmission protocol, the 32-bit message value will contain the actual address and command bytes, as well as their inverses, and that the data is transmitted least significant bit first. The value written to the Data register address must therefore be comprised as follows:

Consider, for example, using the WB_IRRC (in conjunction with an IR Transceiver/Transmitter) to send the "PLAY" command (9Eh or 10011110b) to some target receiver device (a DVD player for example). The address used to target that device is, let's say, A3h (10100011b).

The 32-bit value required to be written to the Data register address, and subsequently loaded into the internal TX_DATA register will be:

Once the value is loaded into the TX_DATA register, the following transmission process occurs:

The txbusy flag in the Status register (STATUS.4) is set, to flag the presence of new data to be transmitted.

The data is then copied into an internal Transmit Shift register (TX_SHIFT). The txbusy flag is then internally acknowledged and cleared.

The message is then transmitted, in accordance with the NEC IR transmission protocol, with the TXD line to the IR Transceiver being pulsed, when required, at the specified modulating carrier frequency (optimally 38.222kHz).

Should you wish to transmit a repeat code – identical to pressing and holding down the same key on a remote control handset – simply write to the Data register address with the same data value and within 108ms since the start of previous message transmission.

If you send a new data message, or send the same data message but outside of 108ms, the data will be copied across to the internal Transmit Shift register and the transmission of a new encoded message frame will commence.

RAW Interface Mode

Let us consider the transmission of IR RC data using the RAW Interface. We will assume that the WB_IRRC has been initialized and set to operate in RAW Interface mode.

Within the software running on the processor, the data to be sent should be passed through an encoding routine to generate the final encoded message.

To transmit data, simply poll the Status register. When the txbusy bit (STATUS.4) is cleared, write the 32-bit value to the WB_IRRC's Data register address – the data will be loaded into the internal TX_DATA register. The 32-bit value should consist of the time (in periods of the carrier frequency) for the required pulse burst (mark), loaded into the high-order word, and also the time (in periods of the carrier frequency) for the subsequent silence (space), loaded into the low-order word.

The value written to the Data register address must therefore be comprised as follows:

Once the value is loaded into the TX_DATA register, the following transmission process occurs:

The txbusy flag in the Status register (STATUS.4) is set, to flag the presence of new data to be transmitted.

The high-order word of the TX_DATA register (TX_DATA(31..16)) is loaded into an internal register HI_COUNT. The low-order word of the TX_DATA register (TX_DATA(15..0)) is loaded into an internal register LO_COUNT. The txbusy flag is then internally acknowledged and cleared.

The pulse burst (mark) portion of the data is transmitted first, with the TXD line to the IR Transceiver being pulsed at the specified modulating carrier frequency until the value in the HI_COUNT register – the required length of the pulse burst in periods of the carrier clock frequency – is reached.

The space portion of the data is then transmitted, essentially silence until the value in the LO_COUNT register – the required length of the space in periods of the carrier clock frequency – is reached.

The next data value written to the TX_DATA register will not be loaded, accordingly, into the HI_COUNT and LO_COUNT registers, until the required length for the space has been reached.