WB_INTERFACE - Operational Overview

The following sections take a closer look at the operation of each of the supported item types – Internal Register, Command Set, External Address Range – with respect to the custom interface. Information on the generated C code is also given.

Internal Register Operation

The internal register item is very similar in operation to a Port I/O component. When active (addressed by the host) it can latch output values to, and read input values from, the connected logic within one clock cycle. Therefore, immediate acknowledgements are automatically sent to the host after a successful operation.

If the register is divided into slices, the data coming from the host on the Wishbone DAT_I bus will be divided into the configured slices and forwarded to the connected logic.
 

 
The following two sections detail what happens during read and write cycles respectively.
 
Read Cycle

The host processor drives CYC_I and STB_I High and presents the address of the register on the ADR_I bus. WE_I is Low.

Within 1 clock cycle:

• The address of the register is decoded

• The register data from the connected logic is put on the DAT_O bus

• ACK_O is driven High

Seeing that the ACK_O signal is High, the processor terminates the read cycle, taking STB_I and CYC_I Low.
 
Write Cycle

The host processor drives CYC_I and STB_I High and presents the address of the register on the ADR_I bus and the data to be sent to the connected logic on the DAT_I bus. WE_I is High.

Within 1 clock cycle:

• The address of the register is decoded

• ACK_O is driven High

• At the next rising edge of CLK_I, the data on the DAT_I bus will be latched into the WB_INTERFACE's internal register(s) and forwarded to the connected logic.

Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low.

Generated C Functions

The following example functions are generated for a sliced internal register item, named BIG. This item is configured for Read and Write, has an 8-bit data width and two register slices - HI (BIG[7..4]) and LO (BIG[3..0]).
 
//------------------------------------------------
// Functions for the register: BIG
//------------------------------------------------

extern uint8_t wb_interface_get_big(
    uint32_t a_addr_base
);

extern uint8_t wb_interface_get_big_lo(
    uint32_t a_addr_base
);

extern uint8_t wb_interface_get_big_hi(
    uint32_t a_addr_base
);

extern void wb_interface_set_big(
    uint32_t a_addr_base,
    uint8_t a_value
);

extern void wb_interface_set_big_slices(
    uint32_t a_addr_base,
    uint8_t lo,
    uint8_t hi
);

For each function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project. For write functions, you will also need to supply the required data value.

There are get and set methods to read/write the entire register – wb_interface_get_big() and wb_interface_set_big().

Additionally, there is a set method which allows you to give separate values for the slices – wb_interface_set_big_slices(). The function will combine the slice values into a single datum and write this to the register.

There are also get methods for the individual slices in the register.

Command Set Operation

The opcode (plus any operands) is written to the command set's address. This is received from the host processor through the DAT_I bus of the Wishbone interface. The opcode is decoded and the selected command's output pin is driven High. The command's operands, if it has any, will be forwarded to the connected logic.

An acknowledgement is sent to the host automatically on the ACK_O line of the Wishbone interface, if the Immediate Acknowledgement option for the command set is enabled. Otherwise, the connected logic needs to send the acknowledgement itself when it is done.

The following section details what happens during a write cycle.
 
Write Cycle

The host processor drives CYC_I and STB_I High and presents the address of the command set on the ADR_I bus, and the opcode + operand on the DAT_I bus. WE_I is High.

Within 1 clock cycle:

• The address of the command set is decoded

• The opcode is decoded

• The selected command's output pin is driven High

• The command's operands (if it has any) are now valid

• ACK_O is driven High if the Immediate Acknowledgement option for the command set item is enabled.

If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available

CSName_ACK_I

pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor.

Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low. The output pin for the command is taken Low and any operands associated with it are no longer valid.

Generated C Functions

The following example function is generated for a command set item, named CHANGE. This item has a 32-bit data width and a single command class – REG. Defined within this class is a single command, BANK, which has an associated 4-bit operand, BANK_NUM.
 
//------------------------------------------------
// Functions for the command set: CHANGE
//------------------------------------------------

extern void wb_interface_set_change_reg_bank(
    uint32_t a_addr_base,
    uint8_t bank_num
);

The above function activates the command BANK. For this function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project. You also need to supply the value for the BANK_NUM operand.

The C code will handle the opcodes.

External Address Range Operation

When the address range item is selected, the RD or WR pin is driven High. The address is also forwarded to the connected logic, and the data is forwarded to or retrieved from that component. The data and address buses to the connected logic are only valid when one of RD or WR is High.

An acknowledgement is sent to the host automatically on the ACK_O line of the Wishbone interface, if the Immediate Acknowledgement option is enabled for the item. Otherwise, the connected logic needs to send the acknowledgement itself when it is done.

The following two sections detail what happens during read and write cycles respectively.
 
Read Cycle

The host processor drives CYC_I and STB_I High and presents an address on the ADR_I bus. WE_I is Low.

Within 1 clock cycle:

• The address code of the external address range is decoded

• The EARName_RD_O pin is driven High

• The address on the EARName_ADR_O bus now becomes valid

• The data from the connected logic on the EARName_DAT_I bus is put on the DAT_O bus

• ACK_O is driven High if the Immediate Acknowledgement option for the external address range item is enabled.

If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available

EARName_ACK_I

pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor.

Seeing that the ACK_O signal is High, the processor terminates the read cycle, taking STB_I and CYC_I Low. The

EARName_RD_O

pin is driven Low and the

EARName_DAT_I

and

EARName_ADR_O

lines are no longer valid.
 
Write Cycle

The host processor drives CYC_I and STB_I High and presents an address on the ADR_I bus data to be sent to the connected logic on the DAT_I bus. WE_I is High.

Within 1 clock cycle:

• The address code of the external address range is decoded

• The EARName_WR_O pin is driven High

• The address on the EARName_ADR_O bus now becomes valid

• The data on the EARName_DAT_O bus now becomes valid

• ACK_O is driven High if the Immediate Acknowledgement option for the external address range item is enabled.

If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available

EARName_ACK_I

pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor.

Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low. The

EARName_WR_O

pin is driven Low and the

EARName_DAT_O

and

EARName_ADR_O

lines are no longer valid.

Generated C Functions

The following example functions are generated for an external address range item, named REG. This item is configured for Read and Write, has a 32-bit data width and a 5-bit address bus.
 
//------------------------------------------------
// Functions for the address range: REG
//------------------------------------------------

extern uint32_t wb_interface_get_reg(
    uint32_t a_addr_base,
    uint32_t a_offset
);

extern void wb_interface_set_reg(
    uint32_t a_addr_base,
    uint32_t a_offset,
    uint32_t a_value
);

For each function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project.

The offset is the address which should be forwarded to the connected logic. There is no need to worry about byte or word addressing, as the C code handles this.