WB_IDE - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the WB_IDE when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the IDE-compatible storage device are made available as sheet entries, associated with the sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_IDE pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_IDE (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I	I	2	Address bus, used to select an internal register of the device for writing to/reading from
DAT_O	O	32	Data to be sent to host processor
DAT_I	I	32	Data received from host processor
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
DMA Interface Signals
M_STB_O	O	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
M_CYC_O	O	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers
M_ACK_I	I	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the connected Wishbone memory device has finished execution of the requested action and the current bus cycle is terminated
M_ADR_O	O	32	Standard Wishbone address bus, used to select an address of the connected Wishbone memory for writing to/reading from
M_DAT_I	I	32	Data received from external Wishbone memory
M_DAT_O	O	32	Data to be sent to external Wishbone memory
M_SEL_O	O	4/High	Select output, used to determine where data is placed on the `M_DAT_O` line during a Write cycle, and from where on the `M_DAT_I` line data is accessed during a Read cycle. For the WB_IDE, only 32-bit data transfers to/from Wishbone memory are supported, meaning that all the lines go High during a Write or Read cycle
M_WE_O	O	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
IDE Device Interface Signals
CS0	O	Low	Chip Select lines – used in conjunction with the Address lines (`A2..A0`) to select the internal register of the IDE device with which to communicate: `CS0` – used to access registers with addresses `1F0` to `1F7` (IDE device's Command Block registers) `CS1` – used to access registers with addresses `3F6` and `3F7` (IDE device's Control Block registers). `CS1` and `CS0` will be set to "00" when the WB_IDE is in powerdown mode, otherwise they will follow the `iders4` and `iders3` bits in the Command register respectively (COMMAND.4 and COMMAND.3).
CS1	O	Low
A0	O	-	Address lines – used, in conjunction with `CS0` and `CS1` to select the internal register or data port of the IDE device with which to communicate. `A2..A0` will be set to "000" when the WB_IDE is in powerdown mode, otherwise they will follow the `iders2`..`iders0` bits in the Command register respectively (COMMAND.2..COMMAND.0).
A1	O	-
A2	O	-
IOWR	O	Low	IDE I/O Write enable. This output will be taken Low if the WB_IDE is in powerdown mode.
IORD	O	Low	IDE I/O Read enable. This output will be taken Low if the WB_IDE is in powerdown mode.
D_DIR	O	Level	Tri-state enable control for the external bidirectional buffer. Low – data from the `D_O` pin is made available on the bidirectional `CF_IDE_D` bus. High – data from the bidirectional `CF_IDE_D` bus is made available at the `D_I` pin.
D_O	O	16	Data Output bus – data to be sent to the IDE-compatible storage device
D_I	I	16	Data Input bus – data retrieved from the IDE-compatible storage device
INTRQ	I	High	IDE Interrupt Request. This signal is currently not used internally by the WB_IDE.
DASP	I	Low	Drive Active/Slave Present. This signal is currently not used internally by the WB_IDE.
DMARQ	I	High	DMA Request. This signal is currently not used internally by the WB_IDE.
IORDY	I	High	IDE I/O Ready. This signal is currently not used internally by the WB_IDE.
IOCS16	I	Low	IDE I/O Channel Select. This signal is currently not used internally by the WB_IDE.
DMACK	O	Low	DMA Acknowledge. This output is normally High. It will be taken Low if the WB_IDE is in powerdown mode.
CSEL	O	Low	Cable Select. This output follows the state of the `csel` bit in the Setup register (SETUP.13). 0 – the IDE device address is 0 (Master) 1 – the IDE device address is 1 (Slave)
RESET	O	Low	Reset line. Taking this signal Low issues a hard reset of the connected IDE-compatible storage device. This output will be taken Low if the WB_IDE is in powerdown mode.
CF_DETECT	I	2/Low	Compact Flash Card Detect. These two signals are used to indicate whether or not a CF card is present in the CF card reader. These signals should both be taken Low when a CF card has been inserted.
CF_POWER	O	Low	Compact Flash Power Enable signal. This line provides an enable signal for controlling power to a Compact Flash card. This signal, which is normally Low, will be taken High if the WB_IDE is in powerdown mode, or if no CF memory card is detected in the CF card reader (`CF_DETECT` = "11"). If using the Desktop NanoBoard NB2DSK01 and the Mass Storage peripheral Board PB02, this signal is wired to the enable pin of a TPS75501 linear voltage regulator on-board the PB02. While this signal is Low, the regulator will be enabled for normal operation, providing 3.3V power to the VCC pins of the corresponding CF card reader on the PB02.
IDE_ACTIVITY	O	High	This line is an inverted copy of the active-Low `DASP` input line to the Controller, and is used to flag connected drive activity.