WB_IDE - Accessible Internal Registers
Contents
The following sections detail the internal registers for the WB_IDE, accessible from the host processor.
Data Register (DATA)
Address: 00
Access: Read & Write except where indicated as Read-only.
Value after Reset: The default value depends on whether the external IDE-compatible storage device is a Compact Flash memory card, and whether that card is inserted into the CF card reader or not:
0000_XXXXh – when CF card not inserted (CF_DETECT = "11")
0002_XXXXh – when CF card is inserted (CF_DETECT = "00")
This register is used to store the 16-bit data to be transmitted to the external IDE-compatible storage device, or to store the data retrieved from that device. It is also used to flag whether the WB_IDE is currently busy or not, and whether a CF memory card has been detected.
Table 1. The DATA register.| MSB LSB | |||
| 31 18 | 17 | 16 | 15 0 |
| - | cfdet | busy | ide_data |
| Bit | Symbol | Function |
|---|---|---|
DATA.31..DATA.18 | - | Not Used. |
DATA.17 (R) | cfdet | Compact Flash Detect flag. When interfacing to the Compact Flash card reader, this bit reflects whether or not a Compact Flash memory card is currently inserted into the reader:
1 – card is inserted (i.e. |
DATA.16 (R) | busy | Busy flag. Used to reflect the current state of the WB_IDE:
1 – WB_IDE is currently busy |
DATA.15..DATA.0 (R/W) | ide_data | Data to be sent to the IDE device during a write. Data received back from the IDE device during a Read. |
Values written to read-only bits in the register (cfdet and busy) will be ignored. All unused bits will return '0' when read.
Command Register (COMMAND)
Address: 01
Access: Write only
Value after Reset: 0000_0000h
This register is used to initiate a command cycle on the external IDE-compatible storage device.
Table 3. The COMMAND register.| MSB LSB | ||||||||
| 31 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | idewr | bsychk | txsec | iders4 | iders3 | iders2 | iders1 | iders0 |
| Bit | Symbol | Function |
|---|---|---|
| COMMAND.31.. COMMAND.8 | - | Not Used. |
| COMMAND.7 | idewr | IDE Write protocol bit. Set this bit to '1' to use a command write protocol. Clear this bit to '0' to use a command read protocol. |
| COMMAND.6 | bsychk | Busy Check bit. Set this bit to '1' to repeatedly read the IDE Status register in the external storage device after a command cycle. Only when the BUSY bit in this register is cleared – flagging that the IDE device has completed the requested Read or Write operation – the busy flag in the WB_IDE's Data register will be cleared (DATA.16). |
| COMMAND.5 | txsec | Transfer Sector bit. Set this bit to '1' to transfer a complete sector (512 bytes) of data in PIO mode, using memory DMA. The direction of transfer is dependent on the idewr bit. |
| COMMAND.4 | iders4 | IDE Register Select bit 4. This bit is connected through to the WB_IDE's CS1 pin. Set this bit to '1' (with the iders3 bit cleared to '0') to select the Control Block registers within the external IDE device. |
| COMMAND.3 | iders3 | IDE Register Select bit 3. This bit is connected through to the WB_IDE's CS0 pin. Set this bit to '1' (with the iders4 bit cleared to '0') to select the Command Block registers within the external IDE device. |
| COMMAND.2 | iders2 | IDE Register Select bits 2..0. These bits are connected through to the WB_IDE's A2..A0 pins respectively. In conjunction with the iders4 and iders3 bits, these bits are used to access the IDE device's internal registers and data ports. |
| COMMAND.1 | iders1 | |
| COMMAND.0 | iders0 |
All bits will return '0' if read.
Memory DMA Start Address Register (MEMSTART)
Address: 10
Access: Read & Write
Value after Reset: XXXX_XXXXh
This register is used to define a starting address in memory from where the next sector (512 bytes) of data will be transferred to the IDE device, when a command write protocol is being performed using memory DMA (idewr bit set in the Command register). If a command read protocol is being performed (idewr bit cleared in the Command register), this address will be the starting point at which transferred data from the IDE device is written.
The address must be located at a 32-bit boundary and therefore the value stored for the start address must be a multiple of 4. Bits 1..0 are therefore always '0'.
Table 5. The MEMSTART register.| MSB LSB | ||
| 31 2 | 1 | 0 |
| start_address | 0 | 0 |
Setup Register (SETUP)
Address: 11
Access: Read & Write.
Value after Reset: 0000_9FFFh
This register is used to setup the PIO command and data transfer timing. It is also used to directly control the state of the CSEL and RESET pins, and to place the WB_IDE in powerdown mode.
| MSB LSB | ||||||
| 31 16 | 15 | 14 | 13 | 12 8 | 7 3 | 2 0 |
| - | pwrdn | rst | csel | pio_recover_dly | pio_rw_dly | pio_setup_dly |
| Bit | Symbol | Function |
|---|---|---|
SETUP.31..SETUP.16 | - | Not Used. |
SETUP.15 | pwrdn | Powerdown bit. When this bit is set ('1') the following outputs are all forced Low:
|
SETUP.14 | rst | Reset bit. Set this bit to '1' to take the WB_IDE's |
SETUP.13 | csel | Cable Select bit. This bit controls the state of the WB_IDE's |
SETUP.12..SETUP.8 | pio_recover_dly | PIO Recover Delay bits. Use these 5 bits to define the recovery delay time. "00000" equates to 1 clock cycle. "11111" equates to 32 clock cycles. Increments are in clock cycles. See PIO timing in the next section. |
SETUP.7..SETUP.3 | pio_rw_dly | PIO Read/Write Delay bits. Use these 5 bits to define the read/write delay time. "00000" equates to 1 clock cycle. "11111" equates to 32 clock cycles. Increments are in clock cycles. See PIO Timing in the next section. |
SETUP.2..SETUP.0 | pio_setup_dly | PIO Setup Delay bits. Use these 3 bits to define the setup delay time. "000" equates to 1 clock cycle. "111" equates to 8 clock cycles. Increments are in clock cycles. See PIO Timing in the next section. |
Note: All unused bits will return '0' when read.
PIO Timing
PIO command and data transfer timing is defined by programming bits 12..0 of the WB_IDE's Setup register. The following timings constitute a PIO data transfer:
- Setup – address valid to IORD/IORW setup time. This is (1 +
pio_setup_dly) cycles
- Pulse – IORD/IORW pulse time. This is (2 +
pio_rw_dly) cycles
- Recovery – IORD/IORW recovery time. This is (2 +
pio_recover_dly) cycles.
The PIO cycle time is by definition:
pulse time + recovery time
Table 7 shows the required minimum IDE PIO timings for each of the PIO modes supported by the WB_IDE.
Table 7. Minimum IDE PIO timings for PIO modes 0 to 4.| Specific Timing | PIO Mode | ||||
|---|---|---|---|---|---|
| Mode 0 | Mode 1 | Mode 2 | Mode 3 | Mode 4 | |
| Setup time | 70ns | 50ns | 30ns | 30ns | 25ns |
| Pulse time | 165ns | 125ns | 100ns | 80ns | 70ns |
| Recovery time | 30ns | 20ns | 15ns | 70ns | 25ns |
| Cycle time | 600ns | 383ns | 240ns | 180ns | 120ns |
Table 8 provides example values to be entered into bits 12..0 of the Setup register, in order to achieve valid timings for PIO modes 0, 2 and 4, when using a 50MHz (20ns) clock. The cycle time is also shown.
Table 8. Example Setup register values to achieve valid PIO timings in modes 0, 2 and 4.| Setup register entry | PIO Mode | ||
|---|---|---|---|
| Mode 0 | Mode 2 | Mode 4 | |
| pio_setup_dly (SETUP(2..0)) | 011 (80ns) | 001 (40ns) | 001 (40ns) |
| pio_rw_dly (SETUP(7..3)) | 00111 (180ns) | 00011 (100ns) | 00010 (80ns) |
| pio_recover_dly (SETUP(12..8)) | 10011 (420ns) | 00101 (140ns) | 00000 (40ns) |
| Cycle time | 600ns | 240ns | 120ns |
The WB_IDE can handle the timing for PIO modes above 2, but does not support IORDY flow control. In practice, all newer drives and Compact Flash memory cards report 120ns as the minimum transfer time allowed for both transfer with and without IORDY flow control. Such storage devices can therefore use PIO mode 4 without enabling IORDY flow control.