WB_FPU - Pin Description
Frozen Content
The following pin description is for the WB_FPU when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces.
Table 1. WB_FPU pin description.| Name | Type | Polarity/ Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External (system) clock signal |
| RST_I | I | High | External (system) reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Floating-point Unit (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | 3 | Address bus, used to select an internal register of the device for writing to/reading from |
| DAT_O | O | 32 | Data to be sent to host processor |
| DAT_I | I | 32 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |