WB_DUALMASTER - Configuration

The WB_DUALMASTER component can be configured after placement on the schematic sheet. Simply right-click and choose the command to configure the component from the pop-up menu that appears (e.g. Configure U_DUALMASTER (WB_DUALMASTER) for a component with designator U_DUALMASTER). Alternatively, click on the Configure button, available in the properties dialog for the component.

The Wishbone Dual-Master Properties dialog will appear, as shown in Figure 1.

Figure 1. Configuring the Dual Master peripheral.

Use the dialog to define the following properties for the device as required.

Type

This region of the dialog enables you to specify the way in which the two Wishbone Masters contest for the slave resource. The following options are available:

• Round Robin – both masters have equal access to the slave

• Priority – one of the masters will have priority access over the other.

Priority

This region of the dialog becomes available if the Priority option is enabled in the Type region and allows you to specify which of the master interfaces for the device (mo or m1) is given the highest priority over access to the slave. The chosen interface is distinguished on the schematic symbol by insertion of the text "High Priority".

Figure 2. Distinguishing the Master
interface that has assigned priority.

Address Bus Width

This region of the dialog allows you to specify the number of address bits required to drive the connected slave device. The width chosen is applied to all interfaces of the WB_DUALMASTER.

When connecting to a single slave memory device – which is connected via the appropriately configured Memory Controller device – you need to set the address bus to the same width as the ADR_I line for the Memory Controller. The Memory Controller will automatically size its ADR_I line according to the size of the physical memory it is connecting to. A Wishbone Interconnect must then be used between the Dual Master and the processor's External Memory Interface, to handle the address line mapping.

When connecting to a bank of physical memory devices through a Wishbone Interconnect, the address bus must be set to 32 Bits - Range = 4GB, which matches the ADR_I line of the Interconnect's master interface.

When connecting to a single slave peripheral device, you need to set the Multi-Master's address bus to the same width as the ADR_I line for the peripheral. A Wishbone Interconnect must then be used between the Dual Master and the processor's Peripheral I/O Interface, to handle the address line mapping.

When connecting to a bank of peripheral devices through a Wishbone Interconnect, the address bus must be set to 24 Bits - Range = 16MB, which matches the ADR_I line of the Interconnect's master interface.

Data Bus Width

This region allows you to specify the resolution of the data bus for the slave device being connected. 8-bit, 16-bit and 32-bit data bus widths are supported. The width chosen is applied to all interfaces of the WB_DUALMASTER.

Space After Master0 Pins

This region of the dialog enables you to alter the amount of blank space that is inserted after the bank of pins for the first Wishbone master interface (prefixed by m0). This allows you to space the two master interfaces appropriately, so that each master device can be directly connected to its corresponding interface, without the need for additional external wiring.