WB_BOOTLOADER_V2 - Operational Overview

Frozen Content

Provided the starting address in SRAM and the size of transfer are both specified in the configuration dialog for the SPI Bootloader, the bootloading functionality will be automatic upon FPGA design download or subsequent system reset. Transfer from the serial Flash memory will always be from address zero.

The bootloading functionality is enabled permanently, through tying the ENABLE input of the component High. For even more flexibility, you could wire this input to a switch, giving you the option to manually enable or disable the bootloading functionality, without having to modify and reprocess your design. On the NB2DSK01 for example, you could wire this input to the DIP-switch, or one of the generic user switches.

The following steps outline the basic procedure in order to initiate serial communications with the target SPI peripheral device, when using the SPI Bootloader component as an SPI Controller.


You will need to re-initialize the Controller after each external reset. This should be carried out in accordance with design requirements and can include:

  • Writing to the Control register with a value that defines the bits as required, including:
    • endian bit (CTRL.5)
    • cpha bit (CTRL.4)
    • cpol bit (CTRL.3)
  • Writing to the Clock Divisor register with the required value for division of the CLK_I signal, to achieve the desired SPI_CLK frequency.

Accessing the Target SPI Device

Before communications between the processor and the required target SPI device can be performed, the FPGA design must first send the address of the target device to the NanoBoard's SPI Controller (specifically a device address register contained therein) and request ownership of the SPI Bus.

Once access to the bus has been granted, the SPI lines from the daughter board FPGA must be routed to the external SPI bus itself, and the select line for the required slave device made active.

This process involves use of the mode and cs bits of the Control register (CTRL.2 and CTRL.1 respectively).

For more detail on the process of opening up an SPI channel for communications with a target SPI device, see NanoBoard SPI Communications - Accessing the SPI Bus from an FPGA Design.

Data Transfer

Once access to the SPI Bus has been granted, the mode of access has been switched to direct communications (mode bit of the Control register '0') and the chip select line taken Low (cs bit in Control register '0') to enable communications with the addressed target device, data transfer can commence.

In order to start the Controller's internal state machine – and hence transmission of data to/reception of data from the target SPI device – simply write the data to be transmitted to the required Data register address, depending on the type of transfer you wish to perform:

  • Write to DATA8 for 8-bit transfer
  • Write to DATA16 for 16-bit transfer
  • Write to DATA32 for 32-bit transfer

The data will be written directly to the Transmit Data register (TX_DATA).

The Controller's state machine will generate the serial clock (SPI_CLK) and manage the data flow as follows:

  • The data to be transmitted will be copied into an internal shift register.
  • The MSB of this data will be shifted out onto the SPI_DOUT line (to the target SPI device). As the state machine is no longer in the IDLE state, the busy flag is set in the Status register (STATUS.0), indicating that the Controller is transmitting.
  • At the same time, a bit of data is received from the target SPI device on the Controller's SPI_DIN line and shifted into bit 0 of the internal shift register.
  • An internal bit counter keeps track of the transmission, which proceeds until all bits of the data to be transmitted have been sent. At this time, the internal shift register holds a data value received from the SPI device.
  • The valid data is loaded from the internal shift register into the Receive Data register (RX_DATA), ready to be read by the host processor.

Read the appropriate Data register address to retrieve the data from the RX_DATA register, in accordance with the type of transfer being performed (8-, 16-, or 32-bit).

SPI communications is, by definition, clock synchronous -– signals change on one edge of the SPI_CLK signal, and the SPI_DIN (MISO) line is stable and sampled on the other edge (depending on polarity and phase settings).

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