WB_BOOTLOADER - Pin Description

Frozen Content

Modified by Admin on Sep 13, 2017

The following pin description is for the WB_BOOTLOADER when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the SPI bus will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_BOOTLOADER pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK	I	Rise	External (system) clock signal
RST	I	High	External (system) reset
ENABLE	I	High	Enable signal. Typically tie this input High (to VCC) to enable bootloading functionality
CPU_HOLD	O	High	CPU Hold signal. This signal should be connected to the processor's RST_I input and provides a separate reset signal to the processor and its connected I/O peripheral devices. All memory devices in the system are still reset using the standard RST signal. This signal ensures that the processor and its I/O slaves are not reset until after the WB_BOOTLOADER has finished copying from the serial Flash memory to the SRAM. This signal will be taken High if the bootloading process is not yet finished, OR if an external reset is received on the component's RST input.
Host Processor Interface Signals
io_STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
io_CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
io_ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_BOOTLOADER (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
io_ADR_I	I	2	Address bus, used to select an internal register of the device for writing to/reading from
io_DAT_O	O	8	Data to be sent to host processor
io_DAT_I	I	8	Data received from host processor
io_WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
io_CLK_I	I	Rise	External (system) clock signal. This signal is identical to the CLK_I input of the processor, and is simply the clock line output as part of the processor's External Peripheral I/O interface.
io_RST_I	I	High	External reset signal. This signal is identical to the RST_I input of the processor, and is simply the reset line output as part of the processor's External Peripheral I/O interface.
io_INT_O	O	High	Interrupt output line. This signal is currently not supported and is grounded internally
SRAM Interface Signals
me_STB_O	O	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
me_CYC_O	O	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers
me_ACK_I	I	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the connected Wishbone memory device has finished execution of the requested action and the current bus cycle is terminated
me_ADR_O	O	20	Standard Wishbone address bus, used to select an address of the connected Wishbone memory for writing to/reading from
me_DAT_I	I	32	Data received from external Wishbone memory
me_DAT_O	O	32	Data to be sent to external Wishbone memory
me_SEL_O	O	4/High	Select output, used to determine where data is placed on the me_DAT_O line during a Write cycle, and from where on the me_DAT_I line data is accessed during a Read cycle. For the WB_BOOTLOADER, only 32-bit data transfers to/from Wishbone memory are supported, meaning that all the lines go High during a Write or Read cycle
me_WE_O	O	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
me_CLK_O	O	Rise	External (system) clock signal (identical to CLK), made available for connecting to the CLK_I input of a slave memory device. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design
me_RST_O	O	High	Reset signal made available for connection to the RST_I input of a slave memory device. This signal goes High when an external reset is issued to the WB_BOOTLOADER on its RST pin. Though not part of the standard Wishbone interface, this signal is provided for convenience when wiring your design
SPI Bus Interface Signals
SPI_DOUT	O	-	Serial Data Out. This is the data written to the target SPI-compatible slave device. Data is shifted into the slave device on the rising edge of the serial clock.
SPI_DIN	I	-	Serial Data In. This is the data read from the target SPI-compatible slave device. Data is shifted out of the slave device on the falling edge of the serial clock
SPI_CLK	O	-	Serial Clock. This signal is generated by the WB_BOOTLOADER and is used to clock data in and out of the slave SPI device.
SPI_MODE	O	Level	Access Mode (when communicating with SPI resources within the Desktop NanoBoard system). When using the WB_BOOTLOADER as a standard SPI Controller, the level of this signal determines whether the FPGA design accesses the NB2DSK01's SPI Controller, or the SPI bus directly: High – communicate with the SPI Controller and, more specifically, an 8-bit SPI device address register therein. Low – communicate directly with a slave device over the SPI bus. This output follows the level of the `mode` bit in the Control/Status register (CSR.2)
SPI_CS	O	Level	Serial Chip Select. When using the WB_BOOTLOADER as a standard SPI Controller, take this signal Low to enable a connected SPI slave device for communications. This output follows the level of the `cs` bit in the Control/Status register (CSR.1)

For detailed information on the SPI communications system in place on the NB2DSK01, and how the SPI_MODE and SPI_CS lines are used, see SPI Communications on the Desktop NanoBoard NB2DSK01.