WB_BOOTLOADER - Operational Overview

Provided the starting address in SRAM and the size of transfer are both specified in the configuration dialog for the SPI Bootloader, the bootloading functionality will be automatic upon FPGA design download or subsequent system reset. Transfer from the serial Flash memory will always be from address zero.
 

 
The following steps outline the basic procedure in order to initiate serial communications with the target SPI peripheral device, when using the SPI Bootloader component as an SPI Controller.

Initialization

After an external reset, you will need to initialize the SPI Bootloader. This should be carried out in accordance with design requirements and can include:

• Writing to the Control/Status register (CSR) and defining:
   
  • The phase and polarity of the SPI_CLK signal, using bits cpha (CSR.4) and cpol (CSR.3) respectively
  • The level of the SPI_MODE signal output, using the mode bit (CSR.2)
  • The level of the SPI_CS signal output, using the cs bit (CSR.1). By default, this bit will be cleared after a reset and therefore in the correct state for enabling the target SPI device.
  • Transmission enable/inhibit, using the txen bit (CSR.0). By default, this bit will be cleared after a reset and therefore in the correct state to enable transmission upon reception of data in the Parallel-to-Serial Data register (DATAOUT). Should you wish to inhibit transmission, set this bit to '1'.
     
• Writing to the Clock Divider register (CDIV) with the required value for division of the CLK signal, to achieve the desired SPI_CLK frequency.

Transmission

In order to start the Controller's internal state machine – and hence transmission of data to/reception of data from the target SPI device – simply write the data to be transmitted into the Parallel-to-Serial Data register (DATAOUT) and ensure that the txen bit in the Control/Status register is '0'.

The Controller's state machine will generate the serial clock (SPI_CLK) and manage the data flow as follows:

• The byte of data to be transmitted will be copied into an internal shift register.

• The MSB of this data will be shifted out onto the SPI_DOUT line (to the target SPI device). As the state machine is no longer in the IDLE state, the busy flag is set (High) in the Control/Status register (CSR.7), indicating that the Controller is transmitting

• At the same time, a bit of data is received from the target SPI device on the Controller's SPI_DIN line and shifted into bit 0 of the internal shift register.

• An internal bit counter keeps track of the transmission, which proceeds until all 8 bits of the data to be transmitted have been sent. At this time, the internal shift register holds an 8-bit data value received from the SPI device.

• The valid byte of data is loaded from the internal shift register into the Serial-to-Parallel Data register (DATAIN), ready to be read by the host processor.