| Name | Type | Polarity/
Bus size | Description |
| Host Processor Interface Signals |
| io_STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| io_CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| io_ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the WB_ASP (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| io_ADR_I | I | 1-32
(see note 1) | Standard Wishbone address bus, used to address parameters of functions implemented in hardware within the WB_ASP. Parameter values are passed to hardware functions from the host processor and return values are read back by the host processor. |
| io_DAT_O | O | 32 | Data to be sent to host processor |
| io_DAT_I | I | 32 | Data received from host processor |
| io_SEL_I | I | 4/High | Select input, used to determine where data is placed on the io_DAT_O line during a Read cycle and from where on the io_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16-, or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24) |
| io_WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle:
0 = Read
1 = Write |
| io_CLK_I | I | Rise | External (system) clock signal. |
| io_RST_I | I | High | External (system) reset signal. |
| External Memory Interface Signals |
| me_STB_O | O | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| me_CYC_O | O | High | Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers |
| me_ACK_I | I | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the connected Wishbone memory device has finished execution of the requested action and the current bus cycle is terminated |
| me_ADR_O | O | 32 | Standard Wishbone address bus, used to select an address of the connected Wishbone memory for writing to/reading from |
| me_DAT_I | I | 32 | Data received from external Wishbone memory |
| me_DAT_O | O | 32 | Data to be sent to external Wishbone memory |
| me_SEL_O | O | 4/High | Select output, used to determine where data is placed on the me_DAT_O line during a Write cycle, and from where on the me_DAT_I line data is accessed during a Read cycle. For the WB_ASP, only 32-bit data transfers to/from Wishbone memory are supported, meaning that all the lines go High during a Write or Read cycle |
| me_WE_O | O | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle:
0 = Read
1 = Write |
| me_CLK_O | O | Rise | External (system) clock signal. This signal is identical to the clock signal arriving at the WB_ASP's io_CLK_I input. This output is provided for wiring convenience. |
| me_RST_O | O | High | External (system) reset signal. This signal will be taken High when an external reset is issued on the WB_ASP's io_RST_I pin. This output is provided for wiring convenience. |