VGA32_TFT Controller - Accessible Internal Registers
Contents
The following sections detail the internal registers for the VGA32_TFT Controller, accessible from the host processor.
Control Register (CTRL)
Address: 0000000000b
Access: Read/Write
Value after Reset: 0000_0000h
This 32-bit register is used to configure and control operation of the Controller.
Table 1. The CTRL register.| MSB LSB | |||||||||||||
| 31 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | ckde | bop | cop | vop | hop | - | - | - | - | - | - | - | vse |
| Bit | Symbol | Function |
|---|---|---|
| CTRL.31..CTRL.13 | - | Not used |
| CTRL.12 | ckde | Clock Division Enable bit |
| CTRL.11 | bop | Blanking Synchronization Output Polarity bit. 0 = Blanking sync pulse is active High |
| CTRL.10 | cop | Composite Synchronization Output Polarity bit. 0 = Composite sync pulse is active High |
| CTRL.9 | vop | Vertical Synchronization Output Polarity bit. 0 = Vertical sync pulse is active High |
| CTRL.8 | hop | Horizontal Synchronization Output Polarity bit. 0 = Horizontal sync pulse is active High |
| CTRL.7 | - | Not used |
| CTRL.6 | - | Not used |
| CTRL.5 | - | Not used |
| CTRL.4 | - | Not used |
| CTRL.3 | - | Not used |
| CTRL.2 | - | Not used |
| CTRL.1 | - | Not used |
| CTRL.0 | vse | Video System Enable bit. 0 = Controller is stopped |
Horizontal Timing Register (HTIM)
This 32-bit non-accessible register is used to define the horizontal timing. The 32-bit value is hard coded to be 0414_00EFh.
Table 3. The HTIM register.| MSB LSB | ||
| 31 24 | 23 16 | 15 0 |
| hsync | hbporch | hvisible |
| Bit | Symbol | Function |
|---|---|---|
HTIM.31..HTIM.24 | hsync | Horizontal Synchronization Pulse length (in pixels - 1). This is hard coded with the value 04h |
HTIM.23..HTIM.16 | hbporch | Horizontal Back Porch length (in pixels - 1). This is hard coded with the value 14h |
HTIM.15..HTIM.0 | hvisible | Horizontal Visible Area (in pixels - 1). This is hard coded with the value 00EFh |
Vertical Timing Register (VTIM)
This 32-bit non-accessible register is used to define the vertical timing. The 32-bit value is hard coded to be 0101_013Fh.
Table 5. The VTIM register.| MSB LSB | ||
| 31 24 | 23 16 | 15 0 |
| vsync | vbporch | vvisible |
| Bit | Symbol | Function |
|---|---|---|
VTIM.31..VTIM.24 | vsync | Vertical Synchronization Pulse length (in lines - 1). This is hard coded with the value 01h |
VTIM.23..VTIM.16 | vbporch | Vertical Back Porch length (in lines - 1). This is hard coded with the value 01h |
VTIM.15..VTIM.0 | vvisible | Vertical Visible Area (in lines - 1). This is hard coded with the value 013Fh |
Horizontal and Vertical Length Register (HVLEN)
This 32-bit non-accessible register is used to store horizontal and vertical length values that together determine the actual extents of the image display area on the screen. The 32-bit value is hard coded to be 0110_0146h.
Table 7. The HVLEN register.| MSB LSB | |
| 31 16 | 15 0 |
| hlen | vlen |
| Bit | Symbol | Function |
|---|---|---|
HVLEN.31..HVLEN.16 | hlen | This value determines the number of viewable pixels to be displayed in each line of a frame and is therefore used to control the horizontal extents of the visible display area. This is hard coded with the value 0110h |
HVLEN.15..HVLEN.0 | vlen | This value determines the number of lines to be displayed in a frame and is therefore used to control the vertical extents of the visible display area. This is hard coded with the value 0146h |
Video Memory Base Address Register (VMBA)
Address: 0000000101b
Access: Read/Write
Value after Reset: 0000_0000h
This 30-bit register is used to store the address in memory at which the video page starts. The width of the memory used to store the graphics to be displayed is actually 32 bits. When addressing locations in this memory, the 30-bit video base address value is sent on the me_ADR_O line as bits 31..2, with bits 1..0 always zeros.
System Clock Division Register (CDIV)
Address: 0000000110b
Access: Read/Write
Value after Reset: 00h
This 8-bit register is used to store a divisor reload value, allowing you to effectively control the frequency of the clock used to drive the timing generation unit (and horizontal and vertical timing sub-units therein).
If you wish to divide CLK_I by 2, load 01h into CDIV. If you wish to divide by 3, load 02h into CDIV, and so on.
If no internal clock division is required, either load 00h into CDIV, or expressly prohibit clock division by clearing the ckde bit in the Control register (CTRL.12).