VGA32_16BPP Controller - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the VGA32_16BPP Controller (configured WB_VGA component) when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. WB_VGA Pin description (configured as VGA32_16BPP Controller).

Name	Type	Polarity / Bus size	Description
Global Control Signals
io_CLK_I	I	Rise	Global Wishbone clock input. This clock is used to drive both Master and Slave interfaces
io_RST_I	I	High	Global Wishbone reset
PixelClock	I	Rise	Video subsystem clock
PixelReset	I	High	Video subsystem reset
Host Processor Interface Signals
io_STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
io_CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
io_ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
io_ADR_I	I	12	Address bus, used to select an internal register of the device for writing to/reading from
io_DAT_O	O	32	Data to be sent to host processor
io_DAT_I	I	32	Data received from host processor
io_SEL_I	I	4/High	Select input, used to determine where data is placed on the io_DAT_O line during a Read cycle and from where on the io_DAT_I line data is accessed during a Write cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24)
io_WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
io_INT_O	O	3/High	Interrupt output lines. Three interrupts are sent to the connected processor on this 3-bit bus. bit 0 = VSYNC bit 1 = HSYNC bit 2 = BLANK
Video Memory Interface Signals
me_STB_O	O	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
me_CYC_O	O	High	Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers
me_ACK_I	I	High	Standard Wishbone device acknowledgement signal. When this signal goes High, the connected Wishbone slave device has finished execution of the requested action and the current bus cycle is terminated
me_ADR_O	O	32	Standard Wishbone address bus. Used to select an address in the connected Wishbone slave device for writing to/reading from
me_DAT_I	I	32	Data received from the connected Wishbone slave device
me_SEL_O	O	4/High	Select output, used to determine where data is placed on the me_DAT_O line during a Write cycle and from where on the me_DAT_I line data is accessed during a Read cycle. Each of the data ports is 32-bits wide with 8-bit granularity, meaning data transfers can be 8-, 16- or 32-bit. The four select bits allow targeting of each of the four active bytes of a port, with bit 0 corresponding to the low byte (7..0) and bit 3 corresponding to the high byte (31..24)
me_WE_O	O	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle. 0 = Read 1 = Write Note: This signal is always Low as the Controller does not write to Video memory, it only reads data from memory.
VGA Monitor Control Signals
HSYNC	O	High/Low	Horizontal synchronization signal. This signal is used to control the horizontal deflection circuit in the VGA monitor, so that the start and end of a line of pixels is correctly displayed across the visible display area of the screen. The polarity of this signal is controlled by the hop bit in the Control register (CTRL.8)
VSYNC	O	High/Low	Vertical synchronization signal. This signal is used to control the vertical deflection circuit in the VGA monitor, so that the start and end of a frame (of lines) is correctly displayed between the top and bottom edges of the visible display area of the screen. The polarity of this signal is controlled by the vop bit in the Control register (CTRL.9)
CSYNC	O	High/Low	Composite synchronization signal. The polarity of this signal is controlled by the cop bit in the Control register (CTRL.10)
BLANK	O	High/Low	Blank synchronization signal. The polarity of this signal is controlled by the bop bit in the Control register (CTRL.11)
R	O	5	Provides the 5-bit digital signal for the intensity of red used in composing a pixel's displayed color
G	O	6	Provides the 6-bit digital signal for the intensity of green used in composing a pixel's displayed color
B	O	5	Provides the 5-bit digital signal for the intensity of blue used in composing a pixel's displayed color.