The FPGA Workspace Map

Frozen Content

At this stage, both FPGA and PCB projects have been created and linked. All ports on the FPGA project are linked, by net name, to the PCB project pins and there are no changes needing to be pushed in either direction. The question now is how to manage any design changes that are made – either in the FPGA project or in the PCB project.

At any given time during the design process, the status of the linking between FPGA and PCB projects can be readily checked, simply by launching the FPGA Workspace Map dialog. Access to this dialog is provided by choosing the command of the same name from the Projects menu, or by pressing the button on the Projects panel.

As illustrated by the example of Figure 1, the dialog displays the relationships (links) between various elements of FPGA and PCB projects and the status of these links – whether the two sides of a link are synchronized and up-to-date or whether some action is required to resynchronize them.

Figure 1. The FPGA Workspace Map dialog (showing linked and fully synchronized FPGA and PCB projects).

The various elements in the two project types are linked in a logical flow – from a soft core processor placed within an FPGA project, to a PCB design document within a linked PCB project. Note that entries in the schematic and/or PCB regions of the PCB project will appear if they contain recognized and supported FPGA components. The Schematic-FPGA Project link, however, will only appear if the FPGA project has been linked to the PCB project.

Each of the links are summarized as follows:

  • FPGA Project - Soft Processor: The Soft Processors region of the dialog is purely added for completeness and offers at-a-glance information on the core processor(s) that are being used in a particular FPGA project. The link, as such, is therefore cosmetic. It will always be displayed as synchronized.
  • Schematic Document (PCB Project) - FPGA Project: This link reflects the synchronized status between the FPGA Component in the PCB project and the appropriate configuration in the FPGA project. When determining the status, the software is looking for any net-related changes.
  • PCB Document - Schematic Document (PCB Project): This link reflects the synchronized status between the FPGA Component footprint on the PCB document and the FPGA Component symbol on the schematic sheet, both within the PCB project.

A link can appear in one of two colors and hovering over a link will produce a textual description of its status:

The Green link signifies up to date (i.e. both sides are synchronized). No action is required.

The Red link signifies that the two sides of the link are not fully synchronized (i.e. a design change has been made on one side but has yet to be passed to the other). Clicking on a Schematic-FPGA Project link with this status will open the Synchronize dialog, from where you can browse and match any unmatched ports and pins.

When two elements of the map are shown to be un-synchronized (i.e. the link between them is red), clicking on the link or its associated icons will give access to a number of synchronization options. The hint that appears when hovering over the link will, where possible, provide information on which directions updates should be made in order to achieve synchronization.

Before passing on any design changes over a link, you can view the differences. Changes are made using Engineering Change Orders (ECOs). From within the FPGA Workspace Map dialog, you have full control over what gets updated and when, all from one convenient location.

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