TSK52x MCU

The TSK52x is an 8-bit embedded controller that executes all ASM51 instructions and is instruction set compatible with the 80C31.

Features-at-a-glance

• Control Unit
   
  • 8-bit Instruction decoder
  • Reduced instruction cycle time up to 12 times.
     
• Arithmetic-Logic Unit
   
  • 8 bit arithmetic and logical operations
  • Boolean manipulations
  • 8 x 8 bit multiplication and 8 / 8 bit division.
     
• 32-bit Input/Output ports
  • Four 8-bit I/O ports
  • Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051.
     
• Interrupt Controller
   
  • Four Priority Levels
  • 7 external interrupts
     
• Internal Data Memory interface
   
  • Can address up to 256 Bytes of Data memory Space.
     
• External Memory interface
   
  • Can address up to 64 KB of external Program memory space
  • Can address up to 64 KB of external Data memory space
  • De-multiplexed Address/Data Bus to allow easy connection to memories
  • Variable length code fetch and MOVC to access fast/slow Program memory
  • Variable length MOVX to access fast/slow RAM or peripherals
     
• Wishbone-compliant ( TSK52B_W and TSK52B_WD only )

Performance

The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. The TSK52x uses 1 clock cycle per machine (instruction) cycle. This leads to a more enhanced and efficient performance with respect to the industry standard 8051 processor working with the same clock frequency (in fact, the execution of instructions is an average eight times faster on the TSK52x).

The standard 8051 has a 12-clock architecture. A machine (instruction) cycle needs 12 clock cycles to execute to completion and most instructions require either one or two machine cycles. Therefore, with the exception of MUL and DIV, the 8051 uses either 12 or 24 clock cycles for each instruction. Furthermore, each cycle in the 8051 uses two memory fetches. In many cases the second fetch is a dummy and extra clock cycles are wasted.

Table 1 below shows the speed advantage of the TSK52x over the standard 8051. A speed advantage of 12 means that the TSK52x performs the same instruction twelve times faster that the 8051.

Table 1. Speed advantage summary.

The average speed advantage is 8.0. However, the real speed improvement seen in any system will depend on the mixture of instructions used.

Availability

The following two variants of the microcontroller are available:

In addition, a corresponding debug-enabled (OCD) version of each variant is also available (TSK52A_D and TSK52B_WD respectively).

These devices can be found in the FPGA Legacy Processors integrated library (FPGA Legacy Processors.IntLib), located in the \Library\Fpga\Legacy Libraries folder of the installation.
 

See Also