TSK3000A Core Instruction - SRA

Frozen Content

Modified by Admin on Sep 13, 2017

Instruction:

Shift Right Arithmetic

Assembler Format:

sra rC, rB, IMM5

Example:

sra $3, $4, 4

Description:

Right-shifts the contents of GPR rB by the number of bits specified by the immediate value, IMM5. The high-order (IMM5) bits become sign-extended and the resulting word is put in GPR rC.

Operation:

rC <-- rB >> IMM5

Instruction Type:

R-Type

Instruction Fields:

rB = Register index of operand B

rC = Register index of destination

IMM5 = 5-bit immediate data value (shift amount)

Encoding:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	rB					rC					IMM5					0	0	0	0	1	1

Latency: 1