TSK3000A Core Instruction - DIVU

Instruction:

Divide Unsigned Word

Assembler Format:

divu rC, rA, rB

Example:

divu $2, $3, $4

Description:

Divides the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit unsigned positive values. The quotient word is loaded into special register LO and also GPR rC. The remainder word is loaded into special register HI. Both quotient and remainder values will always be positive.

If rC is not specified, $0 will be used by default.

Operation:

LO <-- (Unsigned) rA div (Unsigned) rB
rC <-- (Unsigned) rA div (Unsigned) rB
HI <-- (Unsigned) rA mod (Unsigned) rB

Instruction Type:

R-Type

Instruction Fields:

rA = Register index of operand A

rB = Register index of operand B

rC = Register index of destination