TSK3000A Core Instruction - DIV

Instruction:

Divide Word

Assembler Format:

div rC, rA, rB

Example:

div $2, $3, $4

Description:

Divides the contents of GPR rA by the contents of GPR rB, treating both operands as 32-bit two's complement integers. The quotient word is loaded into special register LO and also into GPR rC, the sign of which will be negative if the operands are of opposite signs. The remainder word is loaded into special register HI, the sign of which will be the same as the numerator.

An overflow exception is never raised. If the divisor is zero, the result is undefined.

If rC is not specified, $0 will be used by default.

Ordinarily, instructions are placed after this instruction to check for zero division and overflow.

Operation:

LO <-- rA div rB
rC <-- rA div rB
HI <-- rA mod rB

Instruction Type:

R-Type

Instruction Fields:

rA = Register index of operand A

rB = Register index of operand B

rC = Register index of destination