TSK3000A Core Instruction - ANDI
Frozen Content
Instruction: Bitwise Logical AND Immediate
Assembler Format: andi rB, rA, IMM16
Example: andi $3, $4, 0x1234
Description: Zero-extends the 16-bit immediate value, IMM16, bitwise logically ANDs it with the contents of GPR rA and puts the result in GPR rB.
Operation: rB <-- rA ^ ZeroExtend(IMM16)
Instruction Type: I-Type
Instruction Fields: rA = Register index of operand A
rB = Register index of destination
IMM16 = 16-bit immediate data value
Encoding:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 1 | 0 | 0 | rA | rB | IMM16 | |||||||||||||||||||||||
Latency: 1