TSK3000A Core Instruction - ADD, ADDU
Instruction: Add Word
Assembler Format: add rC, rA, rB
Example: add $3, $4, $5
Description: Adds the contents of GPRs rA and rB and puts the result in GPR rC.
Operation: rC <-- rA + rB
Instruction Type: R-Type
Instruction Fields: rA = Register index of operand A
rB = Register index of operand B
rC = Register index of destination
Encoding:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | rA | rB | rC | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | ||||||||||||
Latency: 1
Notes
The following code example illustrates how overflow detection can be handled, in software, when adding two signed operands:
add rC, rA, rB
xor rD, rC, rA -----compare sign of sum and operand rA
xor rE, rC, rB -----compare sign of sum and operand rB
and rD, rD, rE -----bitwise logically AND the comparison values
slt rD, rD, $0 -----if result less than '0', flag overflow
rD will be set to '1' if an overflow occurred, otherwise it will be set to '0'.