TSK3000A - Relative Branch Instructions
Relative branch instructions change the program flow. These instructions effectively delay the pipeline by one instruction cycle. An instruction inserted into the delay slot (the instruction immediately following a branch instruction) will be executed while the instruction at the branch target address is being fetched.
Branch instructions use the I-type instruction format. Branching is to a relative address, determined by adding a 16-bit signed offset to the Program Counter.
Note: In the following table the IMM16 operand can be an absolute offset or a symbolic address label.
Table 1. Relative Branch Instructions.| Mnemonic | Instruction | Description |
|---|---|---|
BEQ rA, rB, IMM16 | Branch On Equal | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). The contents of GPRs rA and rB are compared and, if equal, the program branches to the target address after a delay of one instruction cycle |
BGEZ rA, IMM16 | Branch On Greater Than Or Equal To Zero | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). If the sign bit of the value in GPR rA is 0 (i.e. the value is positive or 0), the program branches to the target address after a delay of one instruction cycle |
BGEZAL rA, IMM16 | Branch On Greater Than Or Equal To Zero And Link | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). The address of the instruction following the instruction in the delay slot is unconditionally placed in general purpose register r31 as the return address from the branch. If the sign bit of the value in GPR rA is 0 (i.e. the value is positive or 0), the program branches to the target address after a delay of one instruction cycle |
BGTZ rA, IMM16 | Branch On Greater Than Zero | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). If the value in GPR rA is positive (i.e. the sign bit of rA is 0 and the rA value is not 0), the program branches to the target address after a delay of one instruction cycle |
BLEZ rA, IMM16 | Branch On Less Than Or Equal To Zero | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). If the value in GPR rA is negative or 0 (i.e. the sign bit of rA is 1 or the rA value is 0), the program branches to the target address after a delay of one instruction cycle |
BLTZ rA, IMM16 | Branch On Less Than Zero | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). If the value in GPR rA is negative (i.e. the sign bit of rA is 1), the program branches to the target address after a delay of one instruction cycle |
BLTZAL rA, IMM16 | Branch On Less Than Zero And Link | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). The address of the instruction following the instruction in the delay slot is unconditionally placed in general purpose register r31 as the return address from the branch. |
BNE rA, rB, IMM16 | Branch On Not Equal | Generates a branch target address by adding the address of the instruction in the delay slot to a signed offset (16-bit immediate value, IMM16, left-shifted two bits and sign-extended to 32 bits). The contents of GPRs rA and rB are compared and, if not equal, the program branches to the target address after a delay of one instruction cycle |