TSK3000A - Programmable Interval Timer

The TSK3000A includes a programmable interval timer. This is simply a 32-bit counter that is incremented once every clock cycle until it hits the limit value stored in the PIT register. It then resets to zero and starts to count up again.

The value in this counter can not be read and the only evidence of its existence is the interrupt generated (if enabled) when it counts past the value in the PIT register.

The counter runs when the ITE bit of the Status register (Status.8) is High and is reset (held at zero) when ITE is Low. When it equals the limit set in the PIT register, it will return to zero at the next rising clock edge.

The interrupt (if enabled) will appear (flagged) as a pending interrupt on interrupt input 0 (i.e. it is logically ORed with the processor's INT_I[0] input). When the timer is used it is given the highest priority. INT_I[0] should ideally be tied to GND in this case, unless the software application is prepared to handle two types of interrupts on interrupt zero.

When the interrupt occurs, the Interval Timer itself resets (wraps-around to zero) and continues to count. The interrupt flag for the interval timer must be manually cleared however, by writing '1' into the ITR bit of the Status register (Status.7).

Setting up the Interval Timer to Generate Interrupts

The following steps outline the procedure for preparing the Interval Timer for interrupt generation:

• Tie external interrupt 0 to GND (unless the application software can handle two types of interrupt on this interrupt line)

• Disable the Interval Timer by setting ITE bit in the Status register to '0', therefore holding the Timer at zero

• Clear pending interrupts from the Interval Timer, by setting ITR bit in the Status register to '1' and then '0'

• Load the PIT register with the desired time (in clock cycles)

• Enable interrupt 0 by setting bit 0 in the IEnable register to '1'

• Enable the Interval Timer by setting ITE bit in the Status register to '1'. The Timer will start counting up.

After the number of clock cycles programmed into the PIT register, an interrupt will be pending on interrupt 0. If interrupts are enabled (IEc bit in Status register is '1') then the interrupt handler will be called.

Handling an Interrupt Generated by the Interval Timer

When the limit value in the PIT register is reached, the Interval Timer interrupt flag will be set and the Timer itslef will be reset to zero. The interrupt flag will not be reset until you toggle the ITR bit in the Status register to '1' then '0'. The Timer will continue to count up – independent of the state of the ITR bit – resetting whenever it reaches the specified limit, until diabled by clearing the ITE bit in the Status register.

Changing the Rate of Interrupt Generation

To change the rate at which the Interval Timer generates interrupts, simply change the value loaded into the PIT register. The safest way to do this is to carry out the process of preparing the Timer for interrupt generation, as detailed previously, loading the PIT register with the new value.

If you don't disable the Interval Timer first (using the ITE bit to reset and hold it at zero), then if you program a lower value into the PIT register than was previously programmed, the counter may already be past that value and hence will continue all the way up to FFFF_FFFFh until wrapping around.