TSK3000A - Generic Instructions
Frozen Content
Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions (also referred to as pseudo instructions or macros) are defined and supported by the Assembler for the TSK3000A. Each of these generic instructions, as listed in Table 1, translate into one or more separate assembly language instructions (from the core set) in order to fulfill their task.
Note: In Table 1 the following operands are used:
- rA – register index of source operand A
- rB – register index of source operand B
- rC – register index of destination
- IMM5 – 5-bit immediate value
- IMM16 – 16-bit immediate value
- IMM32 – 32-bit immediate value
- target – absolute offset or symbolic address label
- (rA) – address specified by contents of a base register (GPR rA)
- target(rA) – based address (can also be represented as offset(base)). The target address is added to the contents of the base register (GPR rA) to obtain the actual address.
| Mnemonic | Instruction |
|---|---|
| ABS rC, rA | Absolute Value |
| ABS rA | |
| ADD rC, rB | Add |
| ADD rC, rA, IMM32 | |
| ADD rC, IMM32 | |
| ADDI rC, IMM16 | Add Immediate |
| ADDIU rC, IMM16 | Add Immediate Unsigned |
| ADDU rC, rB | Add Unsigned |
| ADDU rC, rA, IMM32 | |
| ADDU rC, IMM32 | |
| AND rC, rB | Bitwise Logical AND |
| AND rC, rA, IMM32 | |
| AND rC, IMM32 | |
| ANDI rC, IMM16 | Bitwise Logical AND Immediate |
| B target | Branch |
| BAL target | Branch And Link |
| BEQ rA, IMM32, target | Branch On Equal |
| BEQZ rA, target | Branch On Equal To Zero |
| BGE rA, rB, target | Branch On Greater Than Or Equal |
| BGE rA, IMM32, target | |
| BGEU rA, rB, target | Branch On Greater Than Or Equal Unsigned |
| BGEU rA, IMM32, target | |
| BGT rA, rB, target | Branch On Greater Than |
| BGT rA, IMM32, target | |
| BGTU rA, rB, target | Branch On Greater Than Unsigned |
| BGTU rA, IMM32, target | |
| BLE rA, rB, target | Branch On Less Than Or Equal To |
| BLE rA, IMM32, target | |
| BLEU rA, rB, target | Branch On Less Than Or Equal To Unsigned |
| BLEU rA, IMM32, target | |
| BLT rA, rB, target | Branch On Less Than |
| BLT rA, IMM32, target | |
| BLTU rA, rB, target | Branch On Less Than Unsigned |
| BLTU rA, IMM32, target | |
| BNE rA, IMM32, target | Branch On Not Equal |
| BNEZ rA, target | Branch On Not Equal To Zero |
| BREAK | Breakpoint |
| DIV rA, rB | Divide |
| DIV rA, IMM32 | |
| DIV rC, rA, IMM32 | |
| DIVU rA, rB | Divide Unsigned |
| DIVU rA, IMM32 | |
| DIVU rC, rA, IMM32 | |
| J rA | Jump |
| JAL rA | Jump And Link |
| JAL rC, target | |
| JALR target | Jump And Link Register |
| JALR rA | |
| JALR rC, target | |
| JR target | Jump Register |
| LA rC, target | Load Address |
| LA rC, target(rA) | |
| LI rC, IMM32 | Load Immediate |
| LB rC, (rA) | Load Byte |
| LB rC, target | |
| LB rC, target(rA) | |
| LBU rC, (rA) | Load Byte Unsigned |
| LBU rC, target | |
| LBU rC, target(rA) | |
| LH rC, (rA) | Load Halfword |
| LH rC, target | |
| LH rC, target(rA) | |
| LHU rC, (rA) | Load Halfword Unsigned |
| LHU rC, target | |
| LHU rC, target(rA) | |
| LW rC, (rA) | Load Word |
| LW rC, target | |
| LW rC, target(rA) | |
| MOVE rC, rA | Move |
| MULT rA, rB | Multiply |
| MULT rA, IMM32 | |
| MULT rC, rA, IMM32 | |
| MULTU rA, rB | Multiply Unsigned |
| MULTU rA, IMM32 | |
| MULTU rC, rA, IMM32 | |
| NEG rC, rA | Negate |
| NEG rA | |
| NEGU rC, rA | Negate Unsigned |
| NEGU rA | |
| NOP | No Operation |
| NOR rC, rB | Bitwise Logical NOR |
| NOR rC, rA, IMM32 | |
| NOR rC, IMM32 | |
| NOT rC, rA | Bitwise Logical NOT |
| NOT rA | |
| OR rC, rB | Bitwise Logical OR |
| OR rC, rA, IMM32 | |
| OR rC, IMM32 | |
| ORI rC, IMM16 | Bitwise Logical OR Immediate |
| ROL rC, rA, IMM5 | Rotate Left |
| ROL rC, rA, rB | |
| ROL rC, IMM5 | |
| ROL rC, rB | |
| ROR rC, rA, IMM5 | Rotate Right |
| ROR rC, rA, rB | |
| ROR rC, IMM5 | |
| ROR rC, rB | |
| SB rC, (rA) | Store Byte |
| SB rC, target | |
| SB rC, target(rA) | |
| SEQ rC, rA, rB | Set On Equal To |
| SEQ rC, rA, IMM32 | |
| SGE rC, rA, rB | Set On Greater Than Or Equal To |
| SGE rC, rA, IMM32 | |
| SGEU rC, rA, rB | Set On Greater Than Or Equal To Unsigned |
| SGEU rC, rA, IMM32 | |
| SGT rC, rA, rB | Set On Greater Than |
| SGT rC, rA, IMM32 | |
| SGTU rC, rA, rB | Set On greater Than Unsigned |
| SGTU rC, rA, IMM32 | |
| SH rC, (rA) | Store Halfword |
| SH rC, target | |
| SH rC, target(rA) | |
| SLA rC, rA, IMM5 | Shift Left Arithmetic |
| SLA rC, rA, rB | |
| SLA rC, IMM5 | |
| SLA rC, rB | |
| SLAV rC, rA, rB | Shift Left Arithmetic Variable |
| SLAV rC, rB | |
| SLE rC, rA, rB | Set On Less Than Or Equal To |
| SLE rC, rA, IMM32 | |
| SLEU rC, rA, rB | Set On Less Than Or Equal To Unsigned |
| SLEU rC, rA, IMM32 | |
| SLL rC, rA, rB | Shift Left Logical |
| SLL rC, IMM5 | |
| SLL rC, rB | |
| SLLV rC, rB | Shift Left Logical Variable |
| SLT rC, rB | Set On Less Than |
| SLT rC, rA, IMM32 | |
| SLT rC, IMM32 | |
| SLTI rC, IMM16 | Set On Less Than Immediate |
| SLTU rC, rB | Set On Less Than Unsigned |
| SLTU rC, rA, IMM32 | |
| SLTU rC, IMM32 | |
| SLTIU rC, IMM16 | Set On Less Than Immediate Unsigned |
| SNE rC, rA, rB | Set On Not Equal To |
| SNE rC, rA, IMM32 | |
| SRA rC, rA, rB | Shift Right Arithmetic |
| SRA rC, IMM5 | |
| SRA rC, rB | |
| SRAV rC, rB | Shift Right Arithmetic Variable |
| SRL rC, rA, rB | Shift Right Logical |
| SRL rC, IMM5 | |
| SRL rC, rB | |
| SRLV rC, rB | Shift Right Logical Variable |
| SUB rC, rB | Subtract |
| SUB rC, rA, IMM32 | |
| SUB rC, IMM32 | |
| SUBU rC, rB | Subtract Unsigned |
| SUBU rC, rA, IMM32 | |
| SUBU rC, IMM32 | |
| SW rC, (rA) | Store Word |
| SW rC, target | |
| SW rC, target(rA) | |
| XOR rC, rB | Bitwise Logical Exclusive OR |
| XOR rC, rA, IMM32 | |
| XOR rC, IMM32 | |
| XORI rC, IMM16 | Bitwise Logical Exclusive OR Immediate |