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The TSK165x is instruction set compatible with the PIC16C5X family. All instructions are single cycle, except for program branches which take two cycles.

Supply of this soft core under the terms and conditions of the Altium End-User License Agreement does not convey nor imply any patent rights to the supplied technologies. Users are cautioned that a license may be required for any use covered by such patent rights.

Features at-a-glance

  • RISC Control Unit
    • Instruction set – comprising all single-word instructions (31 in total)
    • 12-bit instruction decoder
    • Single cycle instruction execution (except double-cycle branch instructions)
    • 7 dedicated special function registers (SFRs)
    • 8-level deep hardware stack
    • Direct, indirect and relative addressing modes for data and instructions
  • Arithmetic Logic Unit
    • 8 bit arithmetic operations
    • 8 bit logical operations
    • Boolean manipulations
  • Device Reset Timer
  • I/O ports
    • TSK165A, TSK165B : 3, 8-bit I/O ports
    • TSK165C : 6, 8-bit I/O ports
  • Data Memory interface
    • TSK165A : can address up to 16+9 bytes of Read/Write Data memory space
    • TSK165B, TSK165C : can address up to 64+9 bytes of Read/Write Data memory space
  • Program Memory interface
    • TSK165A : can address up to 512 bytes of Program memory Space
    • TSK165B, TSK165C : can address up to 2KB of Program memory Space


The high performance of the TSK165x can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the TSK165x uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over the more traditional von Neumann architecture, where program and data are fetched on the same bus. Separating Program and Data memory allows instructions to be sized at 12 bits, rather than the 8-bits used for data.

12-bits wide instruction opcodes make it possible to have all single word instructions. A 12-bit wide Program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps the fetch and execution of instructions. Consequently, all instructions (31 in total) execute in a single cycle except for program branches.


Three variants of the standard microcontroller core are available – the TSK165A, TSK165B and TSK165C respectively. Table 1 summarizes the key differences between the three.

Table 1. TSK165x standard core variants.
Addressable Program memory
Same features as
the TSK165B,
plus three
additional 8-bit
Data memory
16 + 9 bytes
64 + 9 bytes
Program Counter width
9 bits
11 bits
Stack width
9 bits
11 bits

In addition, a corresponding debug-enabled (OCD) version of each variant is also available (TSK165A_D, TSK165B_D and TSK165C_D respectively).

All devices in the TSK165x family can be found in the FPGA Legacy Processors integrated library (FPGA Legacy Processors.IntLib), located in the \Library\Fpga\Legacy Libraries folder of the installation.

A configurable component is also available for this processor type – TSK165 – which can also be found in the FPGA Legacy Processors integrated library.

See Also

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