TERMINAL - Pin Description

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Modified by Admin on Sep 13, 2017

The following pin description is for the device when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface.

Table 1. TERMINAL pin description.

Name	Type	Polarity/ Bus size	Description
Control Signals
CLK_I	I	Rise	External (system) clock signal
RST_I	I	High	External (system) reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the TERMINAL (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I	I	4	Address bus, used to select an internal register of the device for writing to/reading from
DAT_O	O	8	Data to be sent to host processor
DAT_I	I	8	Data received from host processor
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
INT_O	O	2/High	Interrupt output lines. Two interrupts are sent to the connected processor on this 2-bit bus: bit 0 = Goes High if the `txempty` bit in the Interrupt Control register (INTCTRL.1) is set and the `txempty` bit in the Status register (STATUS.1) becomes set bit 1 = Goes High if the `rxnempty` bit in the Interrupt Control register (INTCTRL.5) is set and the `rxnempty` bit in the Status register (STATUS.5) becomes set.