TERMINAL - Interrupts

The Terminal module generates two interrupts – one each catering for the transmit and receive sections of the device. In terms of transmission, an interrupt will be generated if the Transmit Buffer becomes empty – flagging to the processor that there is no data in the buffer to be transmitted for display in the instrument's panel.

In terms of reception, an interrupt will be generated if the Receive Buffer is not empty – flagging to the processor that there is data in the buffer that it needs to read. This means that text has been entered into the instrument's panel, but not all data has been read by the processor.

Transmit Interrupt

To enable this interrupt, the txempty bit of the Interrupt Control register (INTCTRL.1) must be set. When the Transmit Buffer becomes empty, the txempty flag in the Status register will be set and the external interrupt line to the processor – INT_O(0) – will be taken High. The txshempty bit in the Status register (STATUS.3) is also set, although the generation of the interrupt is not dependent on this bit.

This interrupt state is cleared by writing "00000010" to the address for the Interrupt Status register. The result of this operation will be to clear the txempty and txshempty bits in the Status register.

Receive Interrupt

To enable this interrupt, the rxnempty bit of the Interrupt Control register (INTCTRL.5) must be set. When the Receive Buffer remains not empty, the rxnempty flag in the Status register will be set and the external interrupt line to the processor – INT_O(1) – will be taken High. The rxfull bit in the Status register (STATUS.7) is also set, although the generation of the interrupt is not dependent on this bit.

This interrupt state is cleared by writing "00100000" to the address for the Interrupt Status register. The result of this operation will be to clear the rxnempty and rxfull bits in the Status register.