Synchronizing Manually Linked FPGA and PCB Projects

Synchronization of the two linked projects is carried out and maintained by establishing a link between the top-level ports in the FPGA project – specified in the relevant constraint file – and the corresponding pins on the FPGA component schematic. Linking is achieved using the signal name. The name given to the port in the FPGA project must be the same as the net label assigned to the corresponding pin of the schematic component in the PCB project.

When you click on the Schematic-FPGA Project link in the FPGA Workspace Map dialog, the Synchronize dialog will appear (Figure 1).

Figure 1. Use the Synchronize dialog to determine changes required to fully synchronize the linked PCB and FPGA projects.

Note: The Synchronize dialog can be accessed irrespective of the state of the link – fully synchronized or out of date.

How the dialog is populated depends on the extent of net naming in the FPGA component schematic. The following is a summary of the possibilities:

• A net label has been assigned to a pin with the same name as that used for the corresponding port in the FPGA project. The pin number is different to that (if specified) in the associated constraint file and/or the electrical type for the pin is different to that of the port. As the port and pin have the same signal name, they will appear in the Matched Signals list. The entry will be highlighted in red as the pin number and/or electrical type is different.

• A net label has been assigned to a pin with the same name as that used for the corresponding port in the FPGA project. The pin number is identical to that in the associated constraint file and the electrical type for the pin is identical to that of the port. As the port and pin have the same signal name, they will appear in the Matched Signals list. The entry will be highlighted in green as the pin number and electrical type are also the same.

• A net label has been assigned to a pin with a different name to any of the ports in the FPGA project. An entry for the signal name will appear in the Unmatched PCB Signals list.

• All ports that have not been matched to pins with the same name, will appear in the Unmatched FPGA Signals list.

The aim now is to get all ports and pins matched by the same name, pin number and electrical type – i.e. to get the Matched Signals list fully populated and Green.

This is achieved by manually adding and removing nets/ports to/from the PCB project schematic and FPGA project schematic, and changing pin/port electrical properties and pin assignments as required. The Synchronize dialog enables you to create To Do Items so that you can easily remember what needs to be done by checking the To-Do panel.

If the signal naming and electrical types are made identical to start with, the pin numbering can be pushed quickly from one project to the other, depending on whether the master numbering is defined on the PCB or in the constraint file.