PS2_W - Pin Description
Frozen Content
The following pin description is for the PS2_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.
Table 1. PS2_W pin description.| Name | Type | Polarity / Bus size | Description |
|---|---|---|---|
| Control Signals | |||
| CLK_I | I | Rise | External system clock |
| CLK_1MHZ (see note 1) | I | Rise | Reference clock for the generation of timing constants specified within the PS/2 timing specification standard |
| RST_I | I | High | External system reset |
| Host Processor Interface Signals | |||
| STB_I | I | High | Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle |
| CYC_I | I | High | Cycle signal. When asserted, indicates the start of a valid Wishbone cycle |
| ACK_O | O | High | Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated |
| ADR_I | I | Level | Address bus, used to select an internal register of the device for writing to/reading from: 0 = Wishbone Control register (WCREG) |
| DAT_O | O | 8 | Data to be sent to host processor |
| DAT_I | I | 8 | Data received from host processor |
| WE_I | I | Level | Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read |
| INT_O | O | High | Interrupt signal. Used to alert the CPU to the presence of data received from the connected PS/2 device. This signal is asserted for at least 13 periods of CLK_I when 1 byte of data has been received from the PS/2 device. (Note: INT_O will not be asserted if the parity of the byte received is not correct) |
| PS/2 Interface Signals | |||
| PS2CLKTRI | O | Low | Tri-state enable signal for the PS2CLK bidirectional buffer |
| PS2CLKO | O | - | PS2 clock output |
| PS2CLKI | I | - | PS2 clock input |
| PS2DATATRI | O | Low | Tri-state enable signal for the PS2DATA bidirectional buffer |
| PS2DATAO | O | - | PS2 data output (data from the PS2 Controller to the PS/2 device) |
| PS2DATAI | I | - | PS2 data input (data from the PS/2 device to the PS2 Controller) |
To simplify using the bidirectional PSDATA and PSCLK buses, the schematic symbol includes a bus pin for each direction, allowing them to be wired independently. Configuration of bus direction is performed under program control.
Notes
- This clock input signal should ideally be 1MHz. It should, at any rate, be faster than the connected PS/2 device. If this clock signal is too low, the Controller may remain waiting too long for data that might not come from the PS/2 device. If it is too high, the Controller may not wait long enough to correctly receive the data sent from the PS/2 device.