PPC405A Memory Space
The PPC405A uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits.
Memory space is broken into three main areas, as illustrated in Figure 1.
Figure 1. Memory organization in the PPC405A.
These areas are detailed in the following sections.
After a reset, the immersed PPC405 processor performs an instruction fetch from memory location FFFF_FFFCh. In order to make the processor compatible with the address map of the TSK3000A, the PPC405A wrapper provides a no-operation instruction (ORI 0,0,0 opcode 60000000h) in response to this fetch. The effect of executing this instruction is to cause the PC register to increment and wrap around, so that the first user instruction will be fetched from memory location 0000_0000h. This hard-coded instruction has no effect on data access to peripheral memory.
Internal Memory
The internal "Low" or "Boot" RAM is contained within the processor core and is built using true dual-port FPGA block RAM memory. As such, it can be read or written on both sides, simultaneously, in a single cycle.
This memory still has the standard limitation of load delay slots, because the load from memory happens further down the pipeline, after the Execute stage. As a result, any operation that requires loaded data in the cycle immediately after the load will cause the processor to insert a load stall, holding the first half of the pipeline for one cycle while the data becomes available.
Other than this single limitation, the RAM block is as fast as the internal processor registers themselves.
The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the Virtex-II Pro device used. Memory size is configured in the Internal Processor Memory region of the Configure (32-bit Processors) dialog (see Configuring a 32-bit Processor).
Covering the processor's address space between 0000_0000h and 00FF_FFFFh, it will contain the reset and interrupt vectors, as well as any speed or latency-sensitive code or data.
External Memory
The processor's Wishbone External Memory Interface is used by both the instruction and data sides of the processor and provides access to the majority of the address space of the processor. It covers the address space between 0100_0000h and FF00_0000h - 1.
External Memory Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be 'locked' indefinitely, waiting for an acknowledgement on its ME_ACK_I input.
After the ME_STB_O output is taken High a timer built-in to Altium Designer's PPC405A wrapper is started and the 'hard' PPC405, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave memory device, the wait request to the PPC405 is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated.
The ACK_O signal from a slave device should not be used as a 'long delay' hand-shaking mechanism. Where such a mechanism needs to be implemented, either use polling or interrupts.
Peripheral I/O
The processor's Wishbone Peripheral I/O Interface is a one-way Wishbone Master, handling I/O in a very similar way to external memory. The port can be used to communicate with any Wishbone Slave peripheral device and covers the address space between FF00_0000h and FFFF_FFFFh. This address space of 16MB allows a physical address bus size of 24 bits.
Peripheral I/O Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be 'locked' indefinitely, waiting for an acknowledgement on its IO_ACK_I input.
After the IO_STB_O output is taken High a timer built-in to Altium Designer's PPC405A wrapper is started and the 'hard' PPC405, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripheral device, the wait request to the PPC405 is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated.
The ACK_O signal from a slave peripheral should not be used as a 'long delay' hand-shaking mechanism. Where such a mechanism needs to be implemented, either use polling or interrupts.
See Also
For more information on connection of slave physical memory and peripheral I/O devices to the processor's Wishbone interfaces, see Connecting Slave Devices to a 32-bit Processor.