OpenBus Tutorial - Interfacing to the Top-Level Schematic

With the OpenBus System defined, we now need to interface the OpenBus System document with our top-level schematic. This, as has been mentioned previously, is handled through a sheet symbol placed on the schematic sheet.

The sheet entries required to populate the sheet symbol can be obtained through use of the sheet entries and ports synchronization feature. Access this feature through the Sheet Symbol Actions » Synchronize Sheet Entries and Ports command, available from the right-click context menu for the sheet symbol. The Synchronize Ports To Sheet Entries On System dialog will appear (Figure 1).

Figure 1. Use the synchronize sheet entries and ports feature to hook-up the OpenBus System.

All ports from the OpenBus System document will be initially listed as unmatched ports. The ports themselves actually come from two places:

• Ports automatically derived based on the external interfaces of the peripheral devices (I/O peripherals and memory controllers).

• Ports derived from the clock and reset line net definitions in the OpenBus Signal Manager dialog.

When using the dialog to add sheet entries to the sheet symbol, it is a good idea to select each bank of related ports in turn, rather than all ports at once. This will make placement of the sheet entries within the sheet symbol that much easier. Simply group select the required ports and click the Add Sheet Entries button beneath the list – the sheet entries will float on the cursor ready for placement (Figure 2).

Figure 2. Sheet entry placement.

Go ahead and add sheet entries for all existing ports at this time. Once sheet entries for all ports have been added, the sheet symbol will be fully synchronized with the underlying OpenBus System document.

Residual schematic wiring

The last stage required to fully hook the OpenBus System into the FPGA design is to wire-up the external interface circuitry. This is the circuitry that runs between the external interfaces of the peripherals in the OpenBus System, and the physical pins of the FPGA device in which the design will be programmed. It includes any additional logic devices used in the design.

1. Open the original design schematic document, DSF_Mandelbrot.SchDoc.
    
2. Copy the circuitry relating to the VGA 32-Bit TFT Controller device (Figure 3). Do not include the wiring associated with the Controller's master interface as this is already defined as part of the OpenBus System.
    
3. Paste this circuitry into the top-level sheet of our new design, OpenBus_DSF_Mandelbrot.SchDoc.
    

4. Wire this circuitry to the corresponding sheet entries for this peripheral (Figure 3). Note: You may need to rearrange sheet entries for peripheral interfaces in general, in order to match the layout of the port components and thereby make the schematic wiring as neat and as readable as possible.
    
   

   Figure 3. Copying circuitry from the old design to paste and wire in the new design.

   
    

5. Repeat steps 1-4 for each of the following interface circuitry:
   • Circuitry relating to the SPI Controller
   • Circuitry relating to the Parallel Port Unit
   • Circuitry relating to the SRAM Controller.
6. Copy and paste the original circuitry for the external clock and reset lines and then:
   • Delete the CLK and RST net labels
   • Move the circuitry to connect directly into the RST_I sheet entry.
   • Place a new wire from the CLK_BRD side of the FPGA_STARTUP8 device, to the CLK_I sheet entry.
7. Copy and paste the required components for implementation of the Soft JTAG chain (NEXUS_JTAG_CONNECTOR and NEXUS_JTAG_PORT).
    
8. Copy and paste the informational note.

Your final top-level schematic sheet should appear as shown in Figure 4.

Figure 4. Completed top-level schematic.

That's it! – congratulations, you've just built your first FPGA design incorporating an OpenBus System. From here-on-in, the design is identical in behavior to the original schematic-based design. You can test this for yourself by processing the design and downloading to the physical FPGA device resident on the daughter board plug-in of your Desktop NanoBoard NB2DSK01.

This will involve:

• Linking the associated Embedded Software project (Mandelbrot.PrjEmb) and ensuring the Application Memory mapping is defined as required. This mapping is defined as part of the embedded project options, and determines how the mapped physical device memory blocks are used by the embedded software.

• Configuring the FPGA project to target the required physical FPGA device (including assignment of applicable constraint files). This can be achieved most easily using the auto-configuration feature.

• Processing the design using the Devices view (View » Devices View), and downloading the resulting programming file to the target FPGA device on the daughter board.

• Observing the Mandelbrot pattern on the NB2DSK01's TFT LCD panel.

See Also