New Configurable Generic FPGA Logic Components

The Summer 09 release of Altium Designer sees the addition of two new components to the FPGA Configurable Generic integrated library (FPGA Configurable Generic.IntLib) - a clock manager (CLOCK_MANAGER) and a pulse width modulator (PWM).

CLOCK_MANAGER

The new configurable clock manager component enables you to quickly generate a single digital clock output solution based on a specified input clock. For all physical FPGA devices currently targeted by a configuration (or more specifically a constraint file therein) in your FPGA project, the component will output the same clock frequency, where such a frequency is achievable by that device, by setting the device's relevant clock-generation parameters.

Example CLOCK_MANAGER component and configuration dialog, showing which of the targeted devices in a project can achieve a 50MHz output clock, based on a 20MHz input clock.

Simply enter the input frequency (which you wire to the component's CLK input) and then enter the particular output frequency you wish to generate (which will be output on the CLKA pin). You can specify a particular phase for the generated clock signal, and also a permissable tolerance (as some devices may be able to get near to, but not exactly, the frequency you require).

Once your output frequency is specified, simply click the Solve button. An output frequency solution will be calculated and the achievable output frequency for each targeted device listed, allowing you to quickly assess which of the devices are capable of handling the clock frequency you require. The associated clock generation formula parameters are listed – these are the settings used by a particular device to achieve the output frequency.

If a device can't handle the specified clock frequency, it will have no solution, highlighted in red. It is sometimes possible to get a device, which can't readily achieve the required clock frequency, to do so by adjusting the tolerance and clicking Solve again.

A post scaling option is also available. This is typically used where the required output frequency is considerably lower than the input clock – the required output frequency lies outside of the range supported by a device, but can be achieved using additional clock division circuitry. If this is the case, the solution will also specify how much additional clock division is required. You will need to add appropriate clock divider components, sourced from the FPGA Generic integrated library, to handle this.

Output frequencies too low for an FPGA device can be achieved using post scaling. The solution will indicate the clock division required.

PWM

The new configurable pulse width modulator component enables you to quickly generate a PWM-based signal in your design for use as a control signal elsewhere in your ciruit – for example in the control of light intensity for attached LEDs.

As part of its configuration, you can determine:

• The driving input (D[n..0]) – the number of Precision bits used to control the duty cycle.

• A Prescaler – a multiplying value by which to stretch the period of the PWM output signal.

The component's configuration dialog provides at-a-glance information on the proposed period of the PWM signal, based on the driving input (precision), prescaling value and the input clock frequency. Conversely, the number of clock cycles in a single period of the PWM signal is calculated as:

2 Precision x Prescaler

Example PWM component with configuration dialog.