Model Linkage Mechanics

Before looking at the various components available to implement the hardware in your FPGA design, it is worth taking a moment to explore just how vendor-independency is achieved in Altium Designer. EDIF models included with the system for the generic, FPGA-ready (vendor-independent) components are stored in a hierarchy of folders under \Library\Edif, according to vendor and device family.

Figure 1. Pre-synthesized EDIF models allowing for vendor-independent design.

The target physical FPGA device can be changed at any time during the design process and the system will re-link all of the generic component symbols to the relevant pre-synthesized EDIF models for that device, found within these folders. Figure 2 illustrates, generically, the underlying mechanism for this linking – the means to enable vendor independency while placing generic symbols on the OpenBus System or Schematic document.

Figure 2. Mechanism for achieving vendor-independency.

The target device specified in the associated constraint file is used to select the correct folder of EDIF models (for example \Xilinx\Virtex5), and then the component's Design Item ID (schematic) or Designator (OpenBus System) is used to select the EDIF model file from within that folder (e.g. WB_FPU).

As well as system supplied models, user-created pre-synthesized EDIF models are supported. These can be stored in a specified user model folder. User models can also be stored in a hierarchy of folders if you are developing a model for multiple target devices.

The search sequence for EDIF models is:

$project_dir
$user_edif\$vendor\$family
$user_edif\$vendor
$user_edif
$system_edif\$vendor\$family
$system_edif\$vendor
$system_edif