Linked FPGA-PCB Project Changes - Removing a Port from the FPGA Project

You may find that a particular port is no longer required in the design and is subsequently deleted from the FPGA project. There may be existing constraints associated with this port which can be deleted from the constraint file if desired. However, this is not required since they will not be used.

Entering the FPGA Workspace Map dialog will show the Schematic-FPGA Project link as out of date. Clicking the link will open the Synchronize dialog, with an entry for the removed port's corresponding net in the PCB project, in the Unmatched PCB Signals region of the dialog. Figure 1 illustrates this for the removed port TEST_BUTTON.

Figure 1. Newly removed port detected as an unmatched PCB signal.

The signal on the FPGA Component schematic sheet can be removed in much the same way as one was added – either manually, through the use of a To Do Item, or automatically by recreation of the auto-generated schematic sheet, where one exists.

If the sheet was auto-generated (using the FPGA To PCB Project Wizard), the net label and port will be removed from the sheet. It will be marked as an unused I/O pin and configured using the rules set up when the sheet was first generated. If the sheet was not auto-generated, connections to this pin should be removed manually.