Linked FPGA-PCB Project Changes - Pin Swapping in the FPGA Project

Frozen Content

Modified by Admin on Sep 13, 2017

Pin swaps initiated from the FPGA project are likely to be required when a design no longer fits within the FPGA device. The design may fit however, if existing pin constraints are relaxed and the vendor tools are permitted to assign various pin numbers.

The constraint file can be edited to remove any existing pin number constraints as required. Consider for example the following signals which have existing pin assignments, and which are required to have these assignments defined by the vendor tools instead:

For each signal, simply delete the FPGA_PINNUM= part of the record, or the entire record itself, and save the constraint file. Then, from the Devices view, simply compile, synthesize and build the design again. After this process is completed and the design successfully fits again, the new vendor pin file will need to be imported.

With the appropriate constraint file open as the active document, select Import Pin File from the Design menu. The newly created vendor pin file will appear as an entry in the corresponding sub-menu. Importing this file will update the constraints as necessary.

The changes made to the constraint file now need to be pushed back to the PCB project. This is performed from within the FPGA Workspace Map dialog. Entering the FPGA Workspace Map dialog will show the Schematic-FPGA Project link out of date (Red). Clicking on this link will bring up the Synchronize dialog, with the affected pins highlighted in red.

Figure 1. The Synchronize dialog now reflects the pin assignment differences between the linked projects.

Click on the Update To PCB button to push the changes to the PCB project – specifically the FPGA component schematic. The update is performed using an ECO, with the required changes appearing as a series of Move Pins To Different Nets modifications in the Engineering Change Order dialog (Figure 2).

Figure 2. Execution of ECO to resynchronize the FPGA and PCB projects, passing the pin swap data to the FPGA component schematic.

Performing these changes will then make the PCB-Schematic link out of date (if PCB components exist at this stage). Clicking the relevant link will update the PCB document using an ECO, with the required changes appearing as a series of Remove Pins From Nets and Add Pins To Nets modifications in the Engineering Change Order dialog (Figure 3). Note that further changes may still be required to the PCB document if these pins/nets contained any routing.

Figure 3. Execution of ECO to resynchronize the schematic and PCB documents in the PCB project.