Linked FPGA-PCB Project Changes - Configuring IO Standards
FPGA devices generally support a range of I/O standards. These standards follow industry specifications and often include options like LVTTL, LVCMOS and PCI to name a few. This enables the FPGA to communicate directly with other devices requiring a certain standard. Often the standards will also support further customization including the slew rate, current strength and voltage.
Each device will have its own set of supported standards. Only supported standards can be selected for the current device.
There is a complex set of interactions between different I/O standards in an FPGA. Some I/O standards will be able to co-exist while others are mutually exclusive. Often the requirements are limited to I/O banks, such that all pins within an I/O bank on an FPGA must have compatible I/O standards. This becomes particularly important with voltage referenced standards such as GTL, as an I/O bank will generally only be able to support one voltage reference value.
The interaction of selected I/O standards with one another is not modeled here and vendor documentation should be referred to for more detailed information. As a general rule of thumb, keeping pins using different I/O standards in separate I/O banks will ensure compatibility. Any errors will be picked up when the design is processed by the Vendor Place & Route tools.
Selecting Standards
I/O standards, slew rates and drive strengths for each pin of an FPGA device can be defined in the FPGA Signal Manager dialog (Figure 1). This dialog is accessed by choosing the FPGA Signal Manager entry under the Tools menu, from any schematic document within the PCB or FPGA project.
Figure 1. Define I/O standards, slew rates and drive strengths in the FPGA Signal Manager dialog.
When accessed from a schematic in the PCB project, if more than one FPGA component is present a dialog will appear beforehand listing the components from which to choose.
When accessed from a schematic in the FPGA project, if more than one configuration exists in the project that targets the physical device, the Select Configuration dialog will appear beforehand listing all such configurations from which to choose.
Note: The list of available I/O standards are context sensitive – only standards that are applicable for that particular FPGA device will be available.
After defining the characteristics for the appropriate pins of the device as required, click OK to close the dialog. The Engineering Change Order dialog will appear (Figure 2), with the settings you define listed as a series of parameters to be added to the affected port constraint entries in the linked constraint file.
Figure 2. Example generated ECO for changes made to signals in the FPGA Signal Manager dialog.
These changes are to signal characteristics only – not pin-specific changes. As such, they affect only the relevant entries in the associated constraint file. The schematic representation of the FPGA component is not affected and launching the FPGA Workspace Map dialog will show the link between the schematic component and the FPGA project still green, highlighting the fact that the two sides are fully synchronized.
The changes will be stored as constraints on the ports in the constraint file. Each required change will be performed via an ECO and by executing the changes, the new I/O standards will be saved in the constraint file. Any future synthesis/build process will then use these constraints for programming the FPGA. (These constraints would also be used when performing a Signal Integrity analysis on the PCB project).
Related Topics
For a tutorial that looks at how Altium Designer's Signal Integrity Analyzer can be used to determine optimum slew and drive settings for specific pins of an FPGA device, see Tutorial - Checking Signal Integrity on an FPGA Design.