Linked FPGA-PCB Project Changes - Changing FPGA Port Names

If a port name is changed within an FPGA project, or a net label for a pin of the FPGA component in the PCB project is renamed, the FPGA Workspace Map dialog will display the Schematic-FPGA Project link as unsynchronized. This is due to the fact that it is the signal names (net names/port names) that are used to synchronize the projects. The nets cannot be named differently in the PCB and FPGA projects. The same is true of altering the width of a bus.

When a port name is changed on the FPGA side, it is detected in the Synchronize dialog as though a new port has been added and the existing port removed. There will therefore be an entry for the new signal name in the Unmatched FPGA Signals list and an entry for the original signal name in the Unmatched PCB Signals list. Figure 1 illustrates this for a port originally named TEST_BUTTON, which has subsequently been renamed TST_BTN.

Figure 1. Detection of a port whose name has changed from TEST_BUTTON to TST_BTN.

The original signal can simply be renamed, manually, on the FPGA Component schematic sheet in the PCB project. An appropriate Rename Net To Do item for the PCB project can be created as a reminder, simply by clicking the button, to the right of the unmatched signals lists.

In a similar fashion when a net label is renamed for a component pin on the PCB side, it is detected in the Synchronize dialog as though a new net has been added and the existing net removed. There will therefore be an entry for the new signal name in the Unmatched PCB Signals list and an entry for the original signal name in the Unmatched FPGA Signals list.

The original signal can simply be renamed, manually, on the top-level sheet of the FPGA project. An appropriate Rename Port To Do item for the FPGA project can be created as a reminder, simply by clicking the button, to the right of the unmatched signals lists.