Linked FPGA-PCB Project Changes - Adding a Port to the FPGA Project
There may be occasions when it is decided an additional port is required for an FPGA design. The process begins by adding the port to the top-level source schematic sheet in the FPGA project and connecting it as necessary within the design.
Figure 1. Addition of a new port to the top-level schematic of the FPGA design.
The port-to-physical pin assignment must then be made in the relevant constraint file (i.e. the port is mapped to a physical pin of the FPGA device). This can be done by performing the synthesis and build processes in the Devices view during which the vendor tools will assign an available pin to the new port. The vendor pin file should then be imported back into the constraint file. Alternatively a pin number can be manually assigned for the port by editing the constraint file directly. The following shows a constraint record for this new port, mapped to physical pin G18 of the target FPGA device:
Record=Constraint | TargetKind=Port | TargetId=STATUS | FPGA_PINNUM=G18
The design change now needs to be passed on to the PCB project. Entering the FPGA Workspace Map dialog will show the Schematic-FGPA Project link as out of date (Red). The hint text will describe that unmatched signals exist between the FPGA project and the component on the schematic in the PCB project. Clicking the link will open the Synchronize dialog, with an entry for the newly added port in the Unmatched FPGA Signals region of the dialog (Figure 2).
Figure 2. Newly added port detected as an unmatched FPGA signal.
The corresponding net can be added to the FPGA component schematic sheet (in the PCB project) either manually – by creating a To Do Item and adding it at a later stage – or automatically, by regenerating the auto-generated FPGA schematic sheet (where one exists). The following sections take a look at these two methods more closely.
Manually Adding a New Net to the FPGA Component Schematic Sheet
In the Synchronize dialog, click on the Add Nets To PCB button – beneath the Unmatched FPGA Signals list – to create a To Do item entry in the To Do Items region of the dialog (Figure 3).
Figure 3. Creation of a To Do item.
Click the Export To Do Items button – the Set To Do Properties dialog appears (Figure 4). Use this dialog to set a Priority and nominate an Owner for the item.
Figure 4. Defining To Do item properties.
After clicking OK, the new To Do Item will be written and a confirmation dialog will appear to verify this.
The FPGA Workspace Map dialog will still show the Schematic-FPGA Project link as out-of-date (Red). The new net needs now to be added to the schematic sheet for the FPGA component, in the PCB project.
With the FPGA Component schematic sheet open as the active document in the main design window, open the To-Do panel (accessed from the System panels menu, by clicking on the System button at the bottom of the application window). The panel will include an entry to "Add net STATUS" (Figure 5).
Figure 5. The To Do item, exported from the Synchronize dialog, will appear listed in the To-Do panel.
If a physical pin number has already been assigned in the constraint file, for the new port in the FPGA project, you can simply add a net label with the same name as the port, to the corresponding pin of the FPGA component. Ensure that the pin electrical type is set to be the same as the I/O Type specified for the port. Figure 6 illustrates this for the assigned pin G18.
Figure 6. Net label "STATUS" added to pin G18 of the FPGA component and the pin electrical type set to Output.
The port and pin signals will be matched automatically by the fact they have the same net name. The new matched signal entry will appear in the Synchronize dialog. As long as the electrical type for the pin matches that defined for the port, the entry will appear highlighted in Green and the FPGA Workspace Map dialog will show the link as fully synchronized (Green).
If a physical pin number had not been assigned in the constraint file, or no constraint entry had been made at all (the port was added to the FPGA Project schematic alone), simply add the net label to the required pin of the FPGA component (in the PCB project) as detailed previously. The constraint group entry, including the physical pin number parameter can then be passed back to the FPGA project through the Synchronize dialog and subsequent Engineering Change Order dialog.
Figure 7. Passing the required pin information to the constraint file in the FPGA project.
Automatically Adding a New Net to an Auto-generated Schematic Sheet
If the PCB project uses an auto-generated schematic sheet for the FPGA component (created using the FPGA To PCB Project Wizard), you can automatically add a net label and port to the sheet, to correspond with the new port that has been added to the FPGA project.
This is achieved using the Recreate Autogenerated Sheet button, in the Synchronize dialog. After pressing this button, a confirmation dialog will appear, asking whether you wish to proceed with the regeneration of the sheet. Click Yes to proceed with regeneration – the FPGA To PCB Project Wizard will appear.
Run through the pages of the Wizard, setting the options as required and then click Finish. Alternatively, if the Wizard options do not require any changes, simply click the Run With Previous Settings button, on the initial page of the Wizard. The FPGA Component schematic sheet will be recreated, complete with the new net label and its corresponding port.
Figure 8. Recreating an auto-generated sheet will automatically add the required information based on the port in the FPGA project.
Other sheet(s) using a sheet symbol to link to the FPGA component schematic sheet will need to be updated, manually, as appropriate. If an auto-generated sheet was not used, the pin will need to be connected as appropriate.
If a PCB document exists at this stage, the PCB-Schematic link will also now show as being out of date (Red). Pass the changes from the schematic component to the PCB footprint to obtain full synchronicity between the projects.