KEYPADA_W - Pin Description

Frozen Content

Modified by Admin on Sep 13, 2017

The following pin description is for the KEYPADA_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals to the keypad will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. KEYPADA_W Pin description.

Name	Type	Polarity / Bus size	Description
Control Signals
CLK_I	I	Rise	External system clock
CLK_1MHZ	I	Rise	External clock signal. This signal must be 1 MHz in frequency. Clock dividers must be used within the design to achieve this frequency. The initial (undivided) signal can be sourced either from the system (NanoBoard) clock or some other reference clock in the design
RST_I	I	High	External system reset
Host Processor Interface Signals
STB_I	I	High	Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I	I	High	Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O	O	High	Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I	I	Level	Standard Wishbone address bus, used to select an internal register of the slave device for writing to/reading from. 0 = KEYREG 1 = VALKEYREG
DAT_O	O	8	Data to be sent to host microcontroller
WE_I	I	Level	Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write
INT_O	O	High	Interrupt output. This output is connected straight from the VALKEY register. When a key has been detected as being validly pressed on the keypad, the output of this register will be High
Keypad Interface Signals
COL	I	4	Value returned by keypad matrix
ROW	O	4	Driving output to the keypad matrix