KEYPADA_W - Block Diagram

Figure 1 shows a high-level block diagram for the KEYPADA_W component.

Figure 1. KEYPADA_W block diagram.

In the block diagram of Figure 1, only the connection of the KEYREG register output to the DATA_O line has been shown, whereby the 4-bit value Key (representing the row-col intersect for the pressed key) appears as the lower nibble and the high-order nibble grounded, for the data byte sent to the processor. This byte value will be read when the processor addresses the KEYREG register during a Wishbone read cycle (ADR_I = 0).

Similarly, if the processor addresses the VALKEYREG register during a Wishbone read cycle (ADR_I = 1) the output of VALKEYREG will be sent as bit 0 of the data byte to the processor, with the higher 7 bits grounded.

For information on the internal registers for the KEYPADA_W that can be accessed from the host processor, see Accessible Internal Registers.