Import FPGA Changes Wizard - Updating Signal Constraints
The next page of the Import FPGA Project Changes Wizard is used to update signal electrical constraints for the linked signals in the Stub and Master FPGA projects. The electrical characteristics for a signal are defined in the FPGA Signal Manager dialog. For each signal, the page shows entries for IO Standard, Slew Rate and Drive Strength, in both the Stub and Master projects. The information comes directly from the corresponding constraint files for the projects, associated with the chosen configuration if more than one compatible configuration exists.
Where the same signal characteristic is evident in each project, the entries for the Stub and Master columns will be identical and will be non-highlighted. If characteristics for one or more signals differ between the two projects, the entries will be highlighted in red.
Figure 1 illustrates an example whereby the slew rates and drive strengths of audio-based signals have been modified on the PCB side and therefore need to be passed from the Stub FPGA project into the Master FPGA project.
Figure 1. Changes to signal electrical constraints between Stub and Master projects will appear highlighted in Red.
Where such differences exist, the Master project may be updated with information in the Stub project by selecting the signal and clicking the corresponding update button. Again, use Shift+click and Ctrl+click to multi-select.
This will pass the electrical characteristic(s) for the selected signal(s) from the Stub project into the Master project by updating the configuration in the Master project or, more specifically, the relevant constraint file associated to it.
With all the relevant import information determined, the Wizard can now proceed to update the Master FPGA project's top-level schematic and/or relevant constraint file(s) with the design changes from the Stub FPGA project. Simply click on the Finish button to open the Engineering Change Order dialog, listing all modifications to be made in the project (Figure 2). Should you wish, you can enable an option to execute the ECOs quietly – skipping the appearance of the dialog.
Figure 2. Example modifications implementing the design changes imported from the Stub FPGA project.