Getting Started Tutorial - Monitoring the State of Device Pins

Once the design has been downloaded to the FPGA, the Hard Devices chain can be used to monitor the state of the FPGA pins. This is achieved using the device's associated JTAG Viewer panel (accessible from its instrument panel) set to operate in Live Update mode.

Where high-density component packaging makes physical probing of device pins impossible, the JTAG Viewer panel facilitates physical design debugging, 'virtual-style'. It uses the JTAG communications standard to interrogate the state of the pins in any JTAG compliant device in your design, not just the FPGAs. It presents the state of each pin, and includes an image of both the schematic symbol and the footprint, helping you to analyze and debug your design.

Now that we have introduced clock division to slow down the counter, we can observe the activity at the pins of the device much more clearly – so let's go ahead and have a peak 'under the bonnet' as it were.

• From the Devices view, and with the program still running on the FPGA, double-click on the icon for the physical FPGA device in the Hard Devices chain. The Instrument Rack - Hard Devices panel appears (Figure 1).
   
  
  Figure 1. Instrument panel for the physical FPGA device.

• Click the JTAG Viewer Panel button to access the JTAG Viewer panel. Ensure that both Live Update and Hide Unassigned I/O Pin options are enabled (Figure 2).
   
  
  Figure 2. Live monitoring of device pins.

• You are now viewing the pins of the physical FPGA device, while the circuit is in operation. Note how the LED icons light up next to the LEDS() ports as the circuit operates and reflect the distinctive output of the twisted-ring counter. You can also see the corresponding pins on the component symbol and footprint light up, as each pin is made active.

• Change the direction of the count sequence using the NanoBoard's DIP-switch and see the change reflected in the panel.