Getting Started Tutorial - Exploring Design Hierarchy

While the FPGA project file (*PrjFpg) links the various source documents into a single project, the document-to-document and net connective relationships are defined by information in the documents themselves.

In a hierarchical design, the design is partitioned into logical blocks, with each block represented on the top schematic sheet by a sheet symbol. The Filename attribute of each sheet symbol references the underlying design file that it represents. This underlying file can be:

• A schematic sheet

• An OpenBus System document

• A VHDL file

• A Verilog file.

A schematic sub-sheet can also include sheet symbols referencing lower design files. Using this approach a design hierarchy of any depth or complexity can be created.

Hierarchical net and bus connectivity between documents obeys the standard hierarchical project connection behavior, where ports on the sub-document connect to sheet entries of the same name in the sheet symbol that represents that document, as shown for schematic and VHDL sub-documents in Figure 1.

Figure 1. Hierarchical net connectivity is from the sheet entries to matching ports on the document below.

In the base design for our simple counter example, we saw that the synchronous clock signal sourced from the Desktop NanoBoard was too fast. To slow down the counter we will add clock division circuitry. Rather than adding this circuitry to the Simple_Counter schematic, we will capture it in a sub-file (first in a schematic and then in a VHDL file), to demonstrate how hierarchical designs can be used when programming an FPGA.

Clock Division using a Schematic Sub-Sheet

Let's go ahead and capture the clock division circuitry in a schematic sub-sheet.

• Open the schematic document Simple_Counter.SchDoc.

• Place a sheet symbol (Place » Sheet Symbol) initially into free space on the sheet. This sheet symbol will represent the sub-sheet on which our clock division circuitry will be defined.

• Double-click on the sheet symbol and in the Sheet Symbol dialog that appears set the following:
  • Designator: U_Clock_Divider
  • Filename: Clock_Divider.SchDoc.

Figure 2. Sheet symbol referencing the
underlying schematic sub-sheet.

• Add a single sheet entry (Place » Add Sheet Entry) to the left and right of the sheet symbol. Set the following properties:
  • Left-hand sheet entry: Name: CLK_REF, I/O Type: Input
  • Right-hand sheet entry: Name: CLK_OUT, I/O Type: Output

• Wire the sheet symbol into the main circuit and next to the CLK_REF port component, as shown in Figure 3.

Figure 3. Simple_Counter schematic with sheet symbol for Clock_Divider.SchDoc sub-sheet placed and wired.

Now we have our parent sheet symbol, we must create the actual sub-sheet that it references and the required circuitry thereon.

• Right-click on the sheet symbol and choose Sheet Symbol Actions » Create Sheet From Symbol. The new schematic document, Clock_Divider.SchDoc, is created and opened as the active document in the main design window. Initially, this document contains two ports – CLK_REF and CLK_OUT – which correspond (and connect upwards to) the respective sheet entries in the parent sheet symbol.

• Access the Libraries panel and place six clock divider components (CDIV10DC50 - divide by 10 with 50% duty cycle output) from the FPGA Generic integrated library (FPGA Generic.IntLib) onto this new sheet. Connect the components in series and between the two ports as shown in Figure 4.

Figure 4. Clock division circuitry on the schematic sub-sheet Clock_Divider.SchDoc.

• Annotate the components using the Tools » Annotate Schematics Quietly.

• Use File » Save All to save both schematics and the parent project. Accept the default location (i.e. same folder as top-level schematic) when saving Clock_Divider.SchDoc.

• Compile the project to check for any errors. If there are, resolve, save and recompile.

• After compiling, you can check the sheet hierarchy of the project in the Projects panel. The project will now recognize the sub-sheet (Clock_Divider.SchDoc) as a child of the Simple_Counter schematic.

Figure 5. Hieracrhy with a schematic sub-sheet.

Now we have finished adding the clock division circuitry, let's test it out.

• Open the Devices view, ensuring that the Live option is still enabled and the Connection indicator is still Green.

• The physical FPGA device is still programmed and the Process Flow still shows all stages as successfully completed (Green). How so, when we have modified the design's source documents? The answer is in the Ignore FPGA source option, which is disabled by default in Preferences. We need to disable this option so that the modified source documents are taken into account when assessing the status of the Process Flow. When disabled, each stage of the Process Flow will turn Yellow, indicating that it is out of date and must be run again.

Figure 6. Disable the Ignore FPGA source option to take into account modified source when assessing the Process Flow.

• Reprogram the daughter board's FPGA device. The simplest way to do this is to click directly on the Program FPGA stage in the Process Flow. All prior stages will be run automatically in sequence, because they are now marked as out of date. After the synthesis stage, a corresponding intermediate VHDL file for our new schematic sub-sheet will appear in the generated VHDL files for the project.

Figure 7. Additional VHDL file for the sub-sheet,
generated on synthesis.

Once programmed, start the counter (set either switch 7 or switch 8 of the DIP-switch to ON) and observe the output on the NanoBoard's User LEDs has slowed down and we can now see the sequence more clearly. Use the DIP-switch to play with the direction now that it has meaning!

Clock Division using a HDL Sub-File

The concept of design hierarchy can easily be extended when capturing the design using a mixture of schematic sheets and HDL code. A VHDL or Verilog sub-document is referenced in the same way as a schematic sub-sheet, by specifying the sub-document filename in the sheet symbol that represents it.

When referencing a VHDL sub-document, the connectivity is from the sheet symbol to an entity declaration in the VHDL file. To reference an entity with a name that is different from the VHDL filename, include the VHDLEntity parameter in the sheet symbol, whose value is the name of the Entity declared in the VHDL file.

The process is similar when referencing a Verilog sub-document, where the connectivity is from the sheet symbol to a module declaration in the Verilog file. To reference a module with a name that is different from the Verilog filename, include the VerilogModule parameter in the sheet symbol, whose value is the name of the Module declared in the Verilog file.

Let's take a look at substituting the schematic sub-sheet we have just added, with a VHDL file that implements clock division by using a simple delay of one million.

First we will create the VHDL source file.

• Right-click on the Simple_Counter.PrjFpg entry in the Projects panel and choose Add New to Project » VHDL Document. A new VHDL document is created (VHDL1.vhd) and opened as the active document in the main design window. Save this document with the name Clock_Divider.vhd, in the same location as the project file.

• Type the following VHDL code into the document:

   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity Clock_Divider is     port (         CLK_REF : in std_logic;         CLK_OUT : out std_logic     ); end entity;  architecture RTL of Clock_Divider is begin     process(CLK_REF)        variable i : integer range 0 to 999999;     begin        if rising_edge(CLK_REF) then            if i = 0 then                CLK_OUT <= '1';                i := 999999;            else                CLK_OUT <= '0';                i := i - 1;            end if;        end if;     end process; end architecture;

• Save the document

Now we have our VHDL source file, we can create a sheet symbol directly from it. Before we do though, let's remove the existing sheet symbol from the top-level schematic and also its referenced schematic sub-sheet.

• Remove the schematic sub-sheet Clock_Divider.SchDoc from the FPGA project by right-clicking on its name in the Projects panel and choosing Remove from Project from the menu

• Open the Simple_Counter schematic (Simple_Counter.SchDoc). Click on the existing sheet symbol and press the Delete key.

• From the main menus, choose Design » Create Sheet Symbol From Sheet Or HDL. In the Choose Document to Place dialog that appears, select the Clock_Divider.vhd entry and click OK.

• Place and wire the new sheet symbol into the circuit as shown in Figure 8. Notice that the Designator and Filename have been automatically set to U_clock_divider and Clock_Divider.vhd respectively. The VHDLENTITY parameter has also been added, with value = clock_divider (the name of the entity in our VHDL sub-file).

Figure 8. Simple_Counter schematic with sheet symbol for Clock_Divider.vhd sub-file placed and wired.

• Save the schematic and project.

• Compile the project to check for any errors. If there are, resolve them, save and recompile.

• After compiling, you can check the hierarchy of the project in the Projects panel. The project will now recognize the VHDL sub-file (Clock_Divider.vhd) as a child of the Simple_Counter schematic.

Figure 9. Hierarchy with a VHDL sub-file.

Now we have finished adding the VHDL version of the clock division circuitry, let's test it out.

• Open the Devices view and reprogram the daughter board's FPGA device by clicking the Program FPGA stage of the Process Flow.

• Once programmed, start the counter (set either switch 7 or switch 8 of the DIP-switch to ON). You should be able to clearly see the slowed-down counter output on the NanoBoard's User LEDs and control the output via the DIP-switch as before.