FPGA-Specific Constraint - FPGA_DELAY_MAX_TO
Parent article: Constraint Files - FPGA-specific Constraint Elements
Summary: | Sets the maximum delay from register to output port. The place and route tool will attempt not to exceed this delay (but the Vendors do not guarantee this will be the case). |
Values: | Number followed by units (e.g. 10 ns) |
TargetKind: | Port |
Define as: | Constraint file entry |
Vendors: | Actel, Altera, Lattice, Xilinx |
Example
Record=Constraint | TargetKind=Port | TargetId=OUTPUT_PORT | FPGA_DELAY_MAX_TO= 10 ns
Vendor File Translation
The following sections illustrate how this constraint is translated by each of the Vendor tools.
In Xilinx Autogenerated UCF File
INST "OUTPUT_PORT" TNM = TS_MAXDELAY_TARGET_OUTPUT_PORT_PAD;
TIMESPEC TS_MAXDELAY_OUTPUT_PORT = TO "TS_MAXDELAY_TARGET_OUTPUT_PORT_PAD" 10ns;
In Altera Autogenerated TCL File
set_instance_assignment -name TCO_REQUIREMENT -to "OUTPUT_PORT" -entity "DesignTopLevel" 10ns
In Lattice Autogenerated LPF File
MAXDELAY TO PORT "OUTPUT_PORT" 10 ns;
In Actel Autogenerated SDC File
set_max_delay 10 -to {OUTPUT_PORT}