FPGA-Specific Constraint - FPGA_DELAY_MAX
Parent article: Constraint Files - FPGA-specific Constraint Elements
Summary: | Sets the maximum delay from input port to output port. The place and route tool will attempt not to exceed this delay (but the Vendors do not guarantee this will be the case). |
Values: | Number followed by units (e.g. 10 ns) |
TargetKind: | Port |
SourceKind: | Port |
Define as: | Constraint file entry |
Vendors: | Actel, Altera, Lattice, Xilinx |
Example
Record=Constraint | TargetKind=Port | TargetId=VGA_CLK | SourceKind=Port | SourceId=CLK_BRD | FPGA_DELAY_MAX= 10 ns
This constraint record specifies the maximum permissable delay from port CLK_BRD to port VGA_CLK to be 10ns.
Both source and target kinds must be ports. Internal flip-flops are not supported as targets.
Vendor File Translation
The following sections illustrate how this constraint is translated by each of the Vendor tools.
In Xilinx Autogenerated UCF File
INST "CLK_BRD" TNM = TS_MAXDELAY_SOURCE_CLK_BRD_PAD;
INST "VGA_CLK" TNM = TS_MAXDELAY_TARGET_VGA_CLK_PAD;
TIMESPEC TS_MAXDELAY_CLK_BRD_VGA_CLK = FROM "TS_MAXDELAY_SOURCE_CLK_BRD_PAD" TO "TS_MAXDELAY_TARGET_VGA_CLK_PAD" 10ns;
In Altera Autogenerated TCL File
set_instance_assignment -name TPD_REQUIREMENT -from "CLK_BRD" -to "VGA_CLK" -entity "DesignTopLevel" 10ns
In Lattice Autogenerated LPF File
MAXDELAY FROM PORT "CLK_BRD" TO PORT "VGA_CLK" 10 ns;
In Actel Autogenerated SDC File
set_max_delay 10 -from {CLK_BRD} -to {VGA_CLK}