Enabling the Soft Devices JTAG Chain

Frozen Content

Communications from the Altium Designer software environment to embedded processors and virtual instruments in an FPGA design, is carried out over a JTAG communications link. This is referred to on the Desktop NanoBoard as the Soft JTAG (or Nexus) chain.

The Soft JTAG chain signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) are derived in the Desktop NanoBoard's NanoTalk Controller (Xilinx Spartan-3). As part of the communications chain, these signals are wired to four pins of the daughter board FPGA. To interface to these pins, you need to place the NEXUS_JTAG_CONNECTOR design interface component (Figure 1). This can be found in the FPGA NB2DSK01 Port-Plugin integrated library (\Library\Fpga\FPGA NB2DSK01 Port-Plugin.IntLib).

Figure 1. Nexus JTAG Connector.

This component 'brings' the Soft JTAG chain into the design. In order to wire all relevant Nexus-enabled devices (processors, virtual instruments) into this chain, you need to also place a NEXUS_JTAG_PORT component (Figure 2). This component can be found in the FPGA Generic integrated library (\Library\Fpga\FPGA Generic.IntLib).

Figure 2. Nexus Port.

The presence of the NEXUS_JTAG_PORT component instructs the software to wire all components that possess the parameter NEXUS_JTAG_DEVICE=True into the Soft JTAG chain.

Place the NEXUS_JTAG_CONNECTOR and NEXUS_JTAG_PORT components onto the top-level schematic, connecting them together, as shown in Figure 3. Ensure that a VCC Power Port is placed and connected to the TRST input of the NEXUS_JTAG_PORT component.

Figure 3. Connecting JTAG devices into the Soft JTAG chain.

When interfacing to a third party board, these Soft Devices JTAG chain signals must be mapped to physical pins of the FPGA device – the same four pins that are brought out from the device to the general purpose I/O header to which you have wired the physical connections for the Soft Devices JTAG chain.

Working with Multiple FPGAs

The FPGA design environment supports the simultaneous development of FPGAs on multiple NanoBoards or connected user boards. If you have multiple FPGA devices present in the Devices view, you must have a valid design downloaded into each device in order to use the Soft JTAG chain. If one FPGA in this chain includes soft (Nexus-enabled) devices and others do not, each design that does not include soft devices must include the two Soft JTAG implementation components, as described in the previous section. This is because the Soft JTAG chain must route through all target FPGAs, even if an FPGA does not make use of it.

See Also

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