EMAC8_W, EMAC8_MD_W - Operational Overview

The following sections summarize the steps involved in sending and receiving messages using the EMAC8_W or EMAC8_MD_W Controllers.

Initializing the Controller

You will need to re-initialize the Controller, ready for reception of messages, after each external reset. To initialize the Controller:

• Write the 6-Byte MAC Address for the Controller to the MAC_ADDR register. Remember that the most significant byte of the address must be loaded into the least significant byte of the register.

• Start the receiver by setting the srx bit of the CMD register (CMD.1).

Transmitting a Message

To send a message to the connected PHY device:

• Check the txr bit of the STATUS register (STATUS.0). If the Controller is ready to transmit the next message frame, this bit will be High. It is very important to check that the Transmitter has finished sending any previous message frame and is in the ready state, as writing a new message to the Transmit Buffer before the previous message has completed transmission will result in corruption of the previous message.

• Write to the Transmit Buffer with the message that you wish to transmit. Remember that this should include Destination Address, Source Address, Length/Type and Data fields, with all corresponding bytes loaded contiguously into memory.

• Write the length of the message to the TX_LEN register. This is the length, in Bytes, of the message you have just written into the Transmit Buffer.

• Start the Transmitter by setting the stx bit of the CMD register (CMD.0).

The Controller will construct the frame for the message, in accordance with the Ethernet protocol. If configured in Half-Duplex Mode, the Controller will listen to see whether it can transmit – by monitoring its PHY_CRS input. Provided this input is Low, there is no current activity on the Ethernet bus and transmission can go ahead. Transmission is carried out, one nibble at a time, from the PHY_TXD output on each rising edge of the transmit clock provided by the PHY device (arriving at the PHY_TXC input).

When the Controller has completed the transmission, the PHY_TXEN signal will go Low and the txr bit in the STATUS register will go High, signifying that the Transmitter is ready to send the next message frame. If you have enabled the itx bit in the Interrupt Enable register (IE.0), an internal interrupt flag for the transmitter will go High, generating an active interrupt output at the Controller's INT_O pin. The interrupt will be cleared when the STATUS register is read or the device is reset.

Receiving a Message

To receive a message that has been transmitted from the connected PHY device to the Controller:

• Check the rxv bit of the STATUS register (STATUS.1). If the Controller has completed reception of a valid message frame, that message will be loaded into the Receive Buffer and this bit will be High.

• Read the value for the length of the received message from the RX_LEN register. This is the length, in Bytes, for the message currently loaded into the Receive Buffer and includes the Destination Address, Source Address, Length/Type, Data and Padding fields (where applicable).

• Read the message from the Receive Buffer. This will comprise of RX_LEN Bytes of contiguous message data.

• Start the receiver by setting the srx bit of the CMD register (CMD.1). It is important to 'release' the Receive Buffer after the processor has read the message, otherwise no further messages will be received.

When the Receiver has completed reception of a message frame, the PHY_RXDV signal will go Low and the rxv bit in the STATUS register will go High, signifying that the Receiver is ready to receive the next message frame. If you have enabled the irx bit in the Interrupt Enable register (IE.1), an internal interrupt flag for the receiver will go High, generating an active interrupt output at the Controller's INT_O pin. The interrupt will be cleared when the STATUS register is read or the device is reset.