EMAC8_W - Accessible Internal Registers
Contents
The following sections detail the internal registers for the EMAC8_W, that can be indirectly accessed from the host processor. Access to these registers is made using dedicated internal Wishbone registers. See Internal Wishbone Registers for more information.
MAC Address Register (MAC_ADDR)
Address: 5FAh to 5FFh
Access: Write-only
Value after Reset: 000000000000h
This 48-bit register is addressed as six 8-bit locations in memory space. It is used to store the receiver MAC address, which is used by the Receiver to determine if a message on the bus is addressed to it or not (contained within the Destination Address field of the message frame).
This address is not used for transmission. Instead, a separate (and quite possibly different) MAC address must be entered into the Source Address field of a frame to be transmitted.
When writing to the MAC_ADDR register, the most significant byte of the MAC address should be loaded into the least significant byte of the register (at address 5FAh). The least significant byte of the MAC address will therefore be stored in the most significant byte of the register (at address 5FFh).
Status Register (STATUS)
Address: 5F9h
Access: Read-only
Value after Reset: 01h
This 8-bit register is used to determine the current state of the Controller.
Table 1. The STATUS register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | - | - | - | - | - | rxv | txr |
| Bit | Symbol | Function |
|---|---|---|
STATUS.7 | - | Not used. Returns 0 when read |
STATUS.6 | - | Not used. Returns 0 when read |
STATUS.5 | - | Not used. Returns 0 when read |
STATUS.4 | - | Not used. Returns 0 when read |
STATUS.3 | - | Not used. Returns 0 when read |
STATUS.2 | - | Not used. Returns 0 when read |
STATUS.1 | rxv | Receive Valid flag. Reflects the current state of the Receiver.
0 = A message frame has not yet completed reception into the Receive Buffer |
STATUS.0 | txr | Transmit Ready flag. Reflects the current state of the Transmitter.
0 = The Transmitter is still sending the current message frame |
Command Register (CMD)
Address: 5F8h
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to control the start of transmission and reception for the Controller.
Table 3. The CMD register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | - | - | - | - | - | srx | stx |
| Bit | Symbol | Function |
|---|---|---|
CMD.7 | - | Not used. Returns 0 when read |
CMD.6 | - | Not used. Returns 0 when read |
CMD.5 | - | Not used. Returns 0 when read |
CMD.4 | - | Not used. Returns 0 when read |
CMD.3 | - | Not used. Returns 0 when read |
CMD.2 | - | Not used. Returns 0 when read |
CMD.1 | srx | Start Receive bit. Set High to start reception of next message frame |
CMD.0 | stx | Start Transmit bit. Set High to start transmission of next message frame |
Transmit Message Length Register (TX_LEN)
Address: 5F6h to 5F7h
Access: Write-only
Value after Reset: 0000h
This 16-bit register is addressed as two 8-bit locations in memory space. It is used to store the length (in Bytes) of the message frame to be transmitted. This value is used by the Transmitter to determine the number of bytes of data to be read from the Transmitter Buffer, when creating the message frame. The value written to this register is the total of the following individual field lengths:
- Destination Address field – constant value of 6 Bytes
- Source Address field – constant value of 6 Bytes
- Length/Type field – constant value of 2 Bytes
- Data field – variable value in the range 0 to 1500 Bytes.
The Preamble, SFD, Padding and FCS field lengths are not considered as part of this value for the Transmit length.
The maximum value for the Transmit length is 1514 Bytes, which equates to only 11 bits of the TX_LEN register being used. Bits 7..0 of the length value is written to memory location 5F7h, while bits 10..8 are written to the three least significant bits of memory address 5F6h.
The TX_LEN register is mapped to the same address as the RX_LEN register. Provided you are performing a write (WE_I input High), you will access the TX_LEN register.
Receive Message Length Register (RX_LEN)
Address: 5F6h to 5F7h
Access: Read-only
Value after Reset: 0000h
This 16-bit register is addressed as two 8-bit locations in memory space. It is used to store the length (in Bytes) of the received message frame. This value is used by the processor to determine the number of bytes of data to be read from the Receive Buffer. The value read from this register is the total of the following individual field lengths:
- Destination Address field – constant value of 6 Bytes
- Source Address field – constant value of 6 Bytes
- Length/Type field – constant value of 2 Bytes
- Data field – variable value in the range 0 to 1500 Bytes
- Padding field – variable value in the range 0 to 46 Bytes
The Preamble and SFD fields are automatically stripped from the frame upon reception and the FCS field length is not considered as part of this value for the Receive length.
The maximum value for the Receive length is 1514 Bytes, which equates to only 11 bits of the RX_LEN register being used. Bits 7..0 of the length value are written to memory location 5F7h, while bits 10..8 are written to the three least significant bits of memory address 5F6h. The upper five bits of the RX_LEN register (bits 7..3 of address 5F6h) are filled with zeros.
The RX_LEN register is mapped to the same address as the TX_LEN register. Provided you are performing a read (WE_I input Low), you will access the RX_LEN register.
Interrupt Enable Register (IE)
Address: 5F5h
Access: Read and Write
Value after Reset: 00h
This 8-bit register is used to individually enable interrupt generation from the Transmitter and Receiver.
Table 5. The IE register.| MSB LSB | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| - | - | - | - | - | - | irx | itx |
| Bit | Symbol | Function |
|---|---|---|
IE.7 | - | Not used. Returns 0 when read |
IE.6 | - | Not used. Returns 0 when read |
IE.5 | - | Not used. Returns 0 when read |
IE.4 | - | Not used. Returns 0 when read |
IE.3 | - | Not used. Returns 0 when read |
IE.2 | - | Not used. Returns 0 when read |
IE.1 | irx | Receive Interrupt Enable. Set this bit High to enable generation of an interrupt when reception of a message frame has completed and the Receive Buffer is full of valid data, ready to be read |
IE.0 | itx | Transmit Interrupt Enable. Set this bit High to enable generation of an interrupt when the Transmitter has completed transmission of the previously loaded message frame and is waiting ready to transmit the next frame |