EMAC8_MD_W - Pin Description

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The following pin description is for the EMAC8_MD_W when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System.

Table 1. EMAC8_MD_W pin description.
Name
Type
Polarity / Bus size
Description
Control Signals
CLK_I
I
Rise
External (system) clock
RST_I
I
High
External (system) reset
CLK_MD
I
Rise
External clock signal used for the PHY Register Interface. This signal must be less than 1MHz in frequency.
FULL_DPX
I
Level
Duplex select mode:

0 (i.e. connect to GND) = Half Duplex
1 (i.e. connect to VCC) = Full Duplex

Note: Using the Controller in Full Duplex mode results in less FPGA resources being used

Host Processor Interface Signals
STB_I
I
High
Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle
CYC_I
I
High
Cycle signal. When asserted, indicates the start of a valid Wishbone cycle
ACK_O
O
High
Standard Wishbone device acknowledgement signal. When this signal goes high, the Controller (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated
ADR_I
I
2
Address bus, used to select an internal register of the device for writing to/reading from
DAT_O
O
8
Data to be sent to host processor
DAT_I
I
8
Data received from host processor
WE_I
I
Level
Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle:

0 = Read
1 = Write

INT_O
O
High
Interrupt signal. When the corresponding interrupt bits are enabled in the IE register, this signal is used to alert the processor that:
  • the Transmitter has completed transmission of a frame and is ready to transmit the next frame (provided itx bit is set (IE.0))
  • reception of a frame has completed and the Receive Buffer contains valid data to be read (provided irx bit is set (IE.1))
  • the MD interface is ready for the next action (provided imd bit is set (IE.2)).
Media Independent Interface (MII) Interface Signals
PHY_TXD
O
4
Data to be transmitted to the PHY
PHY_TXEN
O
High
Transmit data enable. This signal goes High when transmitting data to the PHY
PHY_TXC
I
Rise
Transmit clock. Used to clock the data that is transmitted to the PHY
PHY_RXD
I
4
Data received from the PHY
PHY_RXDV
I
High
Receive Data Valid signal. This signal goes High if data on the PHY_RXD bus is valid
PHY_RXER
I
High
Receive Error signal. This signal goes High if the PHY detects a receive error
PHY_RXC
I
Rise
Receive clock. Used to clock the data received from the PHY into the Controller
PHY_COL
I
High
Used to flag the detection of a collision
PHY_CRS
I
High
Carrier Sense signal. This signal goes high if the carrier is detected at the network side of the PHY
PHY_RESETB
O
Low
Resets the PHY. This signal is the logical NOT of the RST_I signal. Therefore resetting the Controller will cause a reset of the connected PHY device.
PHY Register Interface Signals
PHY_MDC
O
Rise
PHY register clock
PHY_MDOE
O
Low
Enable signal for the address/data transmitted from the PHY_MDO pin
PHY_MDO
O
1
Address/Data transmitted to PHY registers
PHY_MDI
I
1
Data received from PHY registers
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